Build starting @ 2019-03-05T02:20:36.180592 Running make -C /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid run (with MAKEFLAGS=' -j --jobserver-fds=3,4') --------------------------------------------------------------------------- ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid ++ test 2 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/tiles ++ SPECDIR=build/tiles ++ mkdir -p build/tiles ++ cd build/tiles +++ md5sum +++ cut -c1-8 +++ echo build/tiles ++ export SEED=e37f3fb0 ++ SEED=e37f3fb0 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/build/tiles ++ export SEEDN=tiles ++ SEEDN=tiles + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/generate_tiles.tcl ++ fgrep CRITICAL vivado.log + test -z '' + '[' tiles '!=' tiles ']' + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_001 ++ SPECDIR=build/specimen_001 ++ mkdir -p build/specimen_001 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_001 ++ SPECDIR=build/specimen_001 ++ mkdir -p build/specimen_001 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_001 ++ SPECDIR=build/specimen_001 ++ mkdir -p build/specimen_001 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int ++ '[' -z zynq7 ']' ++ set -ex + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor ++ test 1 -ge 1 ++ cd build/specimen_001 ++ '[' -z zynq7 ']' ++ test '!' -e '' ++ set -ex ++ export SPECDIR=build/specimen_001 ++ SPECDIR=build/specimen_001 ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int ++ mkdir -p build/specimen_001 ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_001 ++ SPECDIR=build/specimen_001 ++ mkdir -p build/specimen_001 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ cd build/specimen_001 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp ++ '[' -z zynq7 ']' ++ set -ex + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int ++ '[' -z zynq7 ']' ++ test 1 -ge 1 ++ set -ex ++ test '!' -e '' ++ export SPECDIR=build/specimen_001 ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp ++ SPECDIR=build/specimen_001 ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp ++ mkdir -p build/specimen_001 ++ test 1 -ge 1 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int ++ test '!' -e '' ++ export SPECDIR=build/specimen_001 ++ SPECDIR=build/specimen_001 ++ cd build/specimen_001 + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ mkdir -p build/specimen_001 ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_001 ++ SPECDIR=build/specimen_001 ++ mkdir -p build/specimen_001 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ cd build/specimen_001 + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh +++ echo build/specimen_001 ++ cd build/specimen_001 ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_001 +++ md5sum ++ SPECDIR=build/specimen_001 ++ mkdir -p build/specimen_001 +++ md5sum +++ cut -c1-8 +++ echo build/specimen_001 +++ cut -c1-8 +++ md5sum +++ echo build/specimen_001 +++ cut -c1-8 ++ cd build/specimen_001 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ cd build/specimen_001 ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram ++ export SEED=ddcf076c ++ test 1 -ge 1 ++ SEED=ddcf076c ++ test '!' -e '' ++ export SPECDIR=build/specimen_001 ++ SPECDIR=build/specimen_001 ++ mkdir -p build/specimen_001 +++ cut -c1-8 ++ export SEED=ddcf076c ++ SEED=ddcf076c ++ cd build/specimen_001 +++ cut -c1-8 +++ md5sum +++ echo build/specimen_001 ++ cd build/specimen_001 +++ echo build/specimen_001 +++ md5sum ++ export SEED=ddcf076c ++ SEED=ddcf076c +++ echo build/specimen_001 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex +++ md5sum ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_001 ++ SPECDIR=build/specimen_001 ++ mkdir -p build/specimen_001 +++ md5sum +++ cut -c1-8 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh +++ cut -c1-8 ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int ++ test 1 -ge 1 ++ test '!' -e '' ++++ pwd ++ export SPECDIR=build/specimen_001 ++ SPECDIR=build/specimen_001 ++ cd build/specimen_001 ++ mkdir -p build/specimen_001 +++ echo build/specimen_001 +++ sed 's/specimen_0*//' +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001 ++++ pwd +++ sed 's/specimen_0*//' +++ md5sum +++ md5sum +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob/build/specimen_001 +++ cut -c1-8 +++ echo build/specimen_001 +++ sed 's/specimen_0*//' ++ export SEED=ddcf076c ++ SEED=ddcf076c +++ cut -c1-8 ++ export SEED=ddcf076c ++ SEED=ddcf076c ++ cd build/specimen_001 ++++ pwd +++ md5sum ++ export SEEDN=1 ++ SEEDN=1 +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/top.py ']' +++ cut -c1-8 +++ echo build/specimen_001 + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/top.py +++ echo build/specimen_001 ++ export SEEDN=1 ++ SEEDN=1 ++ export SEED=ddcf076c + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob/top.py ']' ++ SEED=ddcf076c + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob/top.py +++ sed 's/specimen_0*//' +++ sed 's/specimen_0*//' ++ export SEED=ddcf076c ++ SEED=ddcf076c ++++ pwd ++ export SEEDN=1 ++ SEEDN=1 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/top.py +++ echo build/specimen_001 +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001 ++ cd build/specimen_001 +++ md5sum ++++ pwd ++ export SEED=ddcf076c ++ SEED=ddcf076c +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001 +++ cut -c1-8 ++++ pwd ++ export SEED=ddcf076c ++ export SEED=ddcf076c ++ SEED=ddcf076c ++ SEED=ddcf076c +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_001 ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001 +++ echo build/specimen_001 +++ md5sum ++ export SEEDN=1 ++ SEEDN=1 ++ export SEEDN=1 ++ SEEDN=1 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/top.py + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/top.py ']' +++ cut -c1-8 + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/top.py +++ sed 's/specimen_0*//' +++ sed 's/specimen_0*//' ++ export SEED=ddcf076c ++ SEED=ddcf076c +++ sed 's/specimen_0*//' ++++ pwd ++ export SEEDN=1 ++ SEEDN=1 +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/top.py +++ sed 's/specimen_0*//' ++ export SEED=ddcf076c ++ SEED=ddcf076c +++ sed 's/specimen_0*//' ++ export SEEDN=1 ++ SEEDN=1 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001 +++ sed 's/specimen_0*//' ++ export SEEDN=1 ++ SEEDN=1 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/top.py ']' ++++ pwd + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/top.py +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_001 ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001 ++ export SEEDN=1 ++ SEEDN=1 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/top.py ++ export SEEDN=1 ++ SEEDN=1 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/top.py ++ export SEEDN=1 ++ SEEDN=1 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/top.py +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_001 ++ export SEEDN=1 ++ SEEDN=1 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob/generate.tcl + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/generate.tcl + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/generate.tcl + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/generate.tcl + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/generate.tcl + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl make[3]: *** [build/specimen_001/OK] Error 1 make[2]: *** [iob_int/build/segbits_tilegrid.tdb] Error 2 make[2]: *** Waiting for unfinished jobs.... + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_002 ++ SPECDIR=build/specimen_002 ++ mkdir -p build/specimen_002 ++ cd build/specimen_002 +++ md5sum +++ cut -c1-8 +++ echo build/specimen_002 ++ export SEED=fad8c932 ++ SEED=fad8c932 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_002 ++ export SEEDN=2 ++ SEEDN=2 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/top.py make[3]: *** [build/specimen_001/OK] Error 1 make[2]: *** [iob/build/segbits_tilegrid.tdb] Error 2 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_002 ++ SPECDIR=build/specimen_002 ++ mkdir -p build/specimen_002 ++ cd build/specimen_002 +++ cut -c1-8 +++ echo build/specimen_002 +++ md5sum ++ export SEED=fad8c932 ++ SEED=fad8c932 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002 ++ export SEEDN=2 ++ SEEDN=2 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/generate.tcl + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dframe 15 --dword 0 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_002 ++ SPECDIR=build/specimen_002 ++ mkdir -p build/specimen_002 ++ cd build/specimen_002 +++ echo build/specimen_002 +++ cut -c1-8 +++ md5sum ++ export SEED=fad8c932 ++ SEED=fad8c932 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002 ++ export SEEDN=2 ++ SEEDN=2 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dframe 15 --dword 0 ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 0 --dframe 15 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_002 ++ SPECDIR=build/specimen_002 ++ mkdir -p build/specimen_002 ++ cd build/specimen_002 +++ echo build/specimen_002 +++ cut -c1-8 +++ md5sum ++ export SEED=fad8c932 ++ SEED=fad8c932 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_002 ++ export SEEDN=2 ++ SEEDN=2 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/top.py + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_002 ++ SPECDIR=build/specimen_002 ++ mkdir -p build/specimen_002 ++ cd build/specimen_002 +++ cut -c1-8 +++ echo build/specimen_002 +++ md5sum ++ export SEED=fad8c932 ++ SEED=fad8c932 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002 ++ export SEEDN=2 ++ SEEDN=2 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/generate.tcl + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 1B + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_002 ++ SPECDIR=build/specimen_002 ++ mkdir -p build/specimen_002 ++ cd build/specimen_002 +++ echo build/specimen_002 +++ md5sum +++ cut -c1-8 ++ export SEED=fad8c932 ++ SEED=fad8c932 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002 ++ export SEEDN=2 ++ SEEDN=2 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 0 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_003 ++ SPECDIR=build/specimen_003 ++ mkdir -p build/specimen_003 ++ cd build/specimen_003 +++ echo build/specimen_003 +++ md5sum +++ cut -c1-8 ++ export SEED=131b315d ++ SEED=131b315d +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003 ++ export SEEDN=3 ++ SEEDN=3 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/../fuzzaddr/generate.py --oneval 1 --design params.csv --dframe 1C --dword 53 --dbit 24 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_002 ++ SPECDIR=build/specimen_002 ++ mkdir -p build/specimen_002 ++ cd build/specimen_002 +++ echo build/specimen_002 +++ md5sum +++ cut -c1-8 ++ export SEED=fad8c932 ++ SEED=fad8c932 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_002 ++ export SEEDN=2 ++ SEEDN=2 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 1 --dframe 15 ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 2 --dframe 1B + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_002 ++ SPECDIR=build/specimen_002 ++ mkdir -p build/specimen_002 ++ cd build/specimen_002 +++ echo build/specimen_002 +++ cut -c1-8 +++ md5sum ++ export SEED=fad8c932 ++ SEED=fad8c932 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002 ++ export SEEDN=2 ++ SEEDN=2 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/top.py + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_002 ++ SPECDIR=build/specimen_002 ++ mkdir -p build/specimen_002 ++ cd build/specimen_002 +++ echo build/specimen_002 +++ md5sum +++ cut -c1-8 ++ export SEED=fad8c932 ++ SEED=fad8c932 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002 ++ export SEEDN=2 ++ SEEDN=2 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 0 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_002 ++ SPECDIR=build/specimen_002 ++ mkdir -p build/specimen_002 ++ cd build/specimen_002 +++ cut -c1-8 +++ md5sum +++ echo build/specimen_002 ++ export SEED=fad8c932 ++ SEED=fad8c932 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002 ++ export SEEDN=2 ++ SEEDN=2 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dframe 15 --dword 0 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_003 ++ SPECDIR=build/specimen_003 ++ mkdir -p build/specimen_003 ++ cd build/specimen_003 +++ cut -c1-8 +++ md5sum +++ echo build/specimen_003 ++ export SEED=131b315d ++ SEED=131b315d +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_003 ++ export SEEDN=3 ++ SEEDN=3 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 0 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_003 ++ SPECDIR=build/specimen_003 ++ mkdir -p build/specimen_003 ++ cd build/specimen_003 +++ cut -c1-8 +++ echo build/specimen_003 +++ md5sum ++ export SEED=131b315d ++ SEED=131b315d +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003 ++ export SEEDN=3 ++ SEEDN=3 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 1 --dframe 15 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_003 ++ SPECDIR=build/specimen_003 ++ mkdir -p build/specimen_003 ++ cd build/specimen_003 +++ cut -c1-8 +++ md5sum +++ echo build/specimen_003 ++ export SEED=131b315d ++ SEED=131b315d +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003 ++ export SEEDN=3 ++ SEEDN=3 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dframe 15 --dword 0 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_003 ++ SPECDIR=build/specimen_003 ++ mkdir -p build/specimen_003 ++ cd build/specimen_003 +++ cut -c1-8 +++ echo build/specimen_003 +++ md5sum ++ export SEED=131b315d ++ SEED=131b315d +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_003 ++ export SEEDN=3 ++ SEEDN=3 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 0 --dframe 15 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_003 ++ SPECDIR=build/specimen_003 ++ mkdir -p build/specimen_003 ++ cd build/specimen_003 +++ cut -c1-8 +++ md5sum +++ echo build/specimen_003 ++ export SEED=131b315d ++ SEED=131b315d +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003 ++ export SEEDN=3 ++ SEEDN=3 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 1B + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_003 ++ SPECDIR=build/specimen_003 ++ mkdir -p build/specimen_003 ++ cd build/specimen_003 +++ cut -c1-8 +++ echo build/specimen_003 +++ md5sum ++ export SEED=131b315d ++ SEED=131b315d +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003 ++ export SEEDN=3 ++ SEEDN=3 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 1B + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_004 ++ SPECDIR=build/specimen_004 ++ mkdir -p build/specimen_004 ++ cd build/specimen_004 +++ echo build/specimen_004 +++ cut -c1-8 +++ md5sum ++ export SEED=152d8583 ++ SEED=152d8583 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004 ++ export SEEDN=4 ++ SEEDN=4 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/../fuzzaddr/generate.py --oneval 1 --design params.csv --dframe 1C --dword 53 --dbit 24 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_005 ++ SPECDIR=build/specimen_005 ++ mkdir -p build/specimen_005 ++ cd build/specimen_005 +++ echo build/specimen_005 +++ cut -c1-8 +++ md5sum ++ export SEED=22b443a6 ++ SEED=22b443a6 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005 ++ export SEEDN=5 ++ SEEDN=5 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 1 --dframe 15 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_003 ++ SPECDIR=build/specimen_003 ++ mkdir -p build/specimen_003 ++ cd build/specimen_003 +++ echo build/specimen_003 +++ cut -c1-8 +++ md5sum ++ export SEED=131b315d ++ SEED=131b315d +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003 ++ export SEEDN=3 ++ SEEDN=3 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 2 --dframe 1B + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_004 ++ SPECDIR=build/specimen_004 ++ mkdir -p build/specimen_004 ++ cd build/specimen_004 +++ md5sum +++ cut -c1-8 +++ echo build/specimen_004 ++ export SEED=152d8583 ++ SEED=152d8583 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004 ++ export SEEDN=4 ++ SEEDN=4 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dframe 15 --dword 0 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_004 ++ SPECDIR=build/specimen_004 ++ mkdir -p build/specimen_004 ++ cd build/specimen_004 +++ cut -c1-8 +++ md5sum +++ echo build/specimen_004 ++ export SEED=152d8583 ++ SEED=152d8583 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_004 ++ export SEEDN=4 ++ SEEDN=4 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 0 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_004 ++ SPECDIR=build/specimen_004 ++ mkdir -p build/specimen_004 ++ cd build/specimen_004 +++ md5sum +++ echo build/specimen_004 +++ cut -c1-8 ++ export SEED=152d8583 ++ SEED=152d8583 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004 ++ export SEEDN=4 ++ SEEDN=4 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 1 --dframe 15 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_003 ++ SPECDIR=build/specimen_003 ++ mkdir -p build/specimen_003 ++ cd build/specimen_003 +++ echo build/specimen_003 +++ cut -c1-8 +++ md5sum ++ export SEED=131b315d ++ SEED=131b315d +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003 ++ export SEEDN=3 ++ SEEDN=3 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 0 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_004 ++ SPECDIR=build/specimen_004 ++ mkdir -p build/specimen_004 ++ cd build/specimen_004 +++ echo build/specimen_004 +++ md5sum +++ cut -c1-8 ++ export SEED=152d8583 ++ SEED=152d8583 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004 ++ export SEEDN=4 ++ SEEDN=4 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 2 --dframe 1B + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_004 ++ SPECDIR=build/specimen_004 ++ mkdir -p build/specimen_004 ++ cd build/specimen_004 +++ cut -c1-8 +++ echo build/specimen_004 +++ md5sum ++ export SEED=152d8583 ++ SEED=152d8583 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_004 ++ export SEEDN=4 ++ SEEDN=4 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dframe 15 --dword 0 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_004 ++ SPECDIR=build/specimen_004 ++ mkdir -p build/specimen_004 ++ cd build/specimen_004 +++ md5sum +++ echo build/specimen_004 +++ cut -c1-8 ++ export SEED=152d8583 ++ SEED=152d8583 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004 ++ export SEEDN=4 ++ SEEDN=4 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 0 --dframe 15 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_005 ++ SPECDIR=build/specimen_005 ++ mkdir -p build/specimen_005 ++ cd build/specimen_005 +++ echo build/specimen_005 +++ md5sum +++ cut -c1-8 ++ export SEED=22b443a6 ++ SEED=22b443a6 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005 ++ export SEEDN=5 ++ SEEDN=5 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 1B + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_006 ++ SPECDIR=build/specimen_006 ++ mkdir -p build/specimen_006 ++ cd build/specimen_006 +++ echo build/specimen_006 +++ cut -c1-8 +++ md5sum ++ export SEED=27bbb5c2 ++ SEED=27bbb5c2 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006 ++ export SEEDN=6 ++ SEEDN=6 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 1B + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_007 ++ SPECDIR=build/specimen_007 ++ mkdir -p build/specimen_007 ++ cd build/specimen_007 +++ cut -c1-8 +++ echo build/specimen_007 +++ md5sum ++ export SEED=7ee7ec67 ++ SEED=7ee7ec67 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007 ++ export SEEDN=7 ++ SEEDN=7 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 0 --dframe 15 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_006 ++ SPECDIR=build/specimen_006 ++ mkdir -p build/specimen_006 ++ cd build/specimen_006 +++ echo build/specimen_006 +++ md5sum +++ cut -c1-8 ++ export SEED=27bbb5c2 ++ SEED=27bbb5c2 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006 ++ export SEEDN=6 ++ SEEDN=6 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 1 --dframe 15 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_004 ++ SPECDIR=build/specimen_004 ++ mkdir -p build/specimen_004 ++ cd build/specimen_004 +++ md5sum +++ cut -c1-8 +++ echo build/specimen_004 ++ export SEED=152d8583 ++ SEED=152d8583 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004 ++ export SEEDN=4 ++ SEEDN=4 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 0 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_004 ++ SPECDIR=build/specimen_004 ++ mkdir -p build/specimen_004 ++ cd build/specimen_004 +++ md5sum +++ echo build/specimen_004 +++ cut -c1-8 ++ export SEED=152d8583 ++ SEED=152d8583 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004 ++ export SEEDN=4 ++ SEEDN=4 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dframe 15 --dword 0 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_005 ++ SPECDIR=build/specimen_005 ++ mkdir -p build/specimen_005 ++ cd build/specimen_005 +++ cut -c1-8 +++ md5sum +++ echo build/specimen_005 ++ export SEED=22b443a6 ++ SEED=22b443a6 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005 ++ export SEEDN=5 ++ SEEDN=5 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 0 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_005 ++ SPECDIR=build/specimen_005 ++ mkdir -p build/specimen_005 ++ cd build/specimen_005 +++ md5sum +++ cut -c1-8 +++ echo build/specimen_005 ++ export SEED=22b443a6 ++ SEED=22b443a6 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005 ++ export SEEDN=5 ++ SEEDN=5 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 2 --dframe 1B + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_005 ++ SPECDIR=build/specimen_005 ++ mkdir -p build/specimen_005 ++ cd build/specimen_005 +++ md5sum +++ echo build/specimen_005 +++ cut -c1-8 ++ export SEED=22b443a6 ++ SEED=22b443a6 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005 ++ export SEEDN=5 ++ SEEDN=5 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dframe 15 --dword 0 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_006 ++ SPECDIR=build/specimen_006 ++ mkdir -p build/specimen_006 ++ cd build/specimen_006 +++ md5sum +++ cut -c1-8 +++ echo build/specimen_006 ++ export SEED=27bbb5c2 ++ SEED=27bbb5c2 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006 ++ export SEEDN=6 ++ SEEDN=6 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 0 --dframe 15 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_007 ++ SPECDIR=build/specimen_007 ++ mkdir -p build/specimen_007 ++ cd build/specimen_007 +++ echo build/specimen_007 +++ md5sum +++ cut -c1-8 ++ export SEED=7ee7ec67 ++ SEED=7ee7ec67 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007 ++ export SEEDN=7 ++ SEEDN=7 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/top.py ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 1 --dframe 15 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_005 ++ SPECDIR=build/specimen_005 ++ mkdir -p build/specimen_005 ++ cd build/specimen_005 +++ md5sum +++ cut -c1-8 +++ echo build/specimen_005 ++ export SEED=22b443a6 ++ SEED=22b443a6 ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005 +++ sed 's/specimen_0*//' ++ export SEEDN=5 ++ SEEDN=5 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 1B + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_006 ++ SPECDIR=build/specimen_006 ++ mkdir -p build/specimen_006 ++ cd build/specimen_006 +++ echo build/specimen_006 +++ cut -c1-8 +++ md5sum ++ export SEED=27bbb5c2 ++ SEED=27bbb5c2 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006 ++ export SEEDN=6 ++ SEEDN=6 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 1B + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_008 ++ SPECDIR=build/specimen_008 ++ mkdir -p build/specimen_008 ++ cd build/specimen_008 +++ cut -c1-8 +++ echo build/specimen_008 +++ md5sum ++ export SEED=258dce4a ++ SEED=258dce4a +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008 ++ export SEEDN=8 ++ SEEDN=8 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 0 --dframe 15 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_009 ++ SPECDIR=build/specimen_009 ++ mkdir -p build/specimen_009 ++ cd build/specimen_009 +++ md5sum +++ cut -c1-8 +++ echo build/specimen_009 ++ export SEED=97ca6a42 ++ SEED=97ca6a42 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009 ++ export SEEDN=9 ++ SEEDN=9 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 1 --dframe 15 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_005 ++ SPECDIR=build/specimen_005 ++ mkdir -p build/specimen_005 ++ cd build/specimen_005 +++ md5sum +++ echo build/specimen_005 +++ cut -c1-8 ++ export SEED=22b443a6 ++ SEED=22b443a6 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005 ++ export SEEDN=5 ++ SEEDN=5 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 1 --dframe 15 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_006 ++ SPECDIR=build/specimen_006 ++ mkdir -p build/specimen_006 ++ cd build/specimen_006 +++ cut -c1-8 +++ echo build/specimen_006 +++ md5sum ++ export SEED=27bbb5c2 ++ SEED=27bbb5c2 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006 ++ export SEEDN=6 ++ SEEDN=6 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 0 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_006 ++ SPECDIR=build/specimen_006 ++ mkdir -p build/specimen_006 ++ cd build/specimen_006 +++ md5sum +++ echo build/specimen_006 +++ cut -c1-8 ++ export SEED=27bbb5c2 ++ SEED=27bbb5c2 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006 ++ export SEEDN=6 ++ SEEDN=6 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 0 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_006 ++ SPECDIR=build/specimen_006 ++ mkdir -p build/specimen_006 ++ cd build/specimen_006 +++ echo build/specimen_006 +++ md5sum +++ cut -c1-8 ++ export SEED=27bbb5c2 ++ SEED=27bbb5c2 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006 ++ export SEEDN=6 ++ SEEDN=6 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 0 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_007 ++ SPECDIR=build/specimen_007 ++ mkdir -p build/specimen_007 ++ cd build/specimen_007 +++ cut -c1-8 +++ md5sum +++ echo build/specimen_007 ++ export SEED=7ee7ec67 ++ SEED=7ee7ec67 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007 ++ export SEEDN=7 ++ SEEDN=7 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 2 --dframe 1B + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_007 ++ SPECDIR=build/specimen_007 ++ mkdir -p build/specimen_007 ++ cd build/specimen_007 +++ echo build/specimen_007 +++ cut -c1-8 +++ md5sum ++ export SEED=7ee7ec67 ++ SEED=7ee7ec67 ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007 +++ sed 's/specimen_0*//' ++ export SEEDN=7 ++ SEEDN=7 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 2 --dframe 1B + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_007 ++ SPECDIR=build/specimen_007 ++ mkdir -p build/specimen_007 ++ cd build/specimen_007 +++ cut -c1-8 +++ echo build/specimen_007 +++ md5sum ++ export SEED=7ee7ec67 ++ SEED=7ee7ec67 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007 ++ export SEEDN=7 ++ SEEDN=7 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 0 --dframe 15 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_008 ++ SPECDIR=build/specimen_008 ++ mkdir -p build/specimen_008 ++ cd build/specimen_008 +++ cut -c1-8 +++ echo build/specimen_008 +++ md5sum ++ export SEED=258dce4a ++ SEED=258dce4a +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008 ++ export SEEDN=8 ++ SEEDN=8 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 1B + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_010 ++ SPECDIR=build/specimen_010 ++ mkdir -p build/specimen_010 ++ cd build/specimen_010 +++ echo build/specimen_010 +++ md5sum +++ cut -c1-8 ++ export SEED=2cd8f4a9 ++ SEED=2cd8f4a9 ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010 +++ sed 's/specimen_0*//' ++ export SEEDN=10 ++ SEEDN=10 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 1B + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_007 ++ SPECDIR=build/specimen_007 ++ mkdir -p build/specimen_007 ++ cd build/specimen_007 +++ echo build/specimen_007 +++ md5sum +++ cut -c1-8 ++ export SEED=7ee7ec67 ++ SEED=7ee7ec67 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007 ++ export SEEDN=7 ++ SEEDN=7 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 1 --dframe 15 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_008 ++ SPECDIR=build/specimen_008 ++ mkdir -p build/specimen_008 ++ cd build/specimen_008 +++ echo build/specimen_008 +++ md5sum +++ cut -c1-8 ++ export SEED=258dce4a ++ SEED=258dce4a +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008 ++ export SEEDN=8 ++ SEEDN=8 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 1 --dframe 15 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_011 ++ SPECDIR=build/specimen_011 ++ mkdir -p build/specimen_011 ++ cd build/specimen_011 +++ md5sum +++ echo build/specimen_011 +++ cut -c1-8 ++ export SEED=e53d240d ++ SEED=e53d240d +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011 ++ export SEEDN=11 ++ SEEDN=11 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/top.py ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 1 --dframe 15 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_008 ++ SPECDIR=build/specimen_008 ++ mkdir -p build/specimen_008 ++ cd build/specimen_008 +++ echo build/specimen_008 +++ cut -c1-8 +++ md5sum ++ export SEED=258dce4a ++ SEED=258dce4a +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008 ++ export SEEDN=8 ++ SEEDN=8 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 0 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_008 ++ SPECDIR=build/specimen_008 ++ mkdir -p build/specimen_008 ++ cd build/specimen_008 +++ echo build/specimen_008 +++ cut -c1-8 +++ md5sum ++ export SEED=258dce4a ++ SEED=258dce4a +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008 ++ export SEEDN=8 ++ SEEDN=8 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 1 --dframe 15 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_007 ++ SPECDIR=build/specimen_007 ++ mkdir -p build/specimen_007 ++ cd build/specimen_007 +++ cut -c1-8 +++ md5sum +++ echo build/specimen_007 ++ export SEED=7ee7ec67 ++ SEED=7ee7ec67 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007 ++ export SEEDN=7 ++ SEEDN=7 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 0 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_008 ++ SPECDIR=build/specimen_008 ++ mkdir -p build/specimen_008 ++ cd build/specimen_008 +++ cut -c1-8 +++ echo build/specimen_008 +++ md5sum ++ export SEED=258dce4a ++ SEED=258dce4a +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008 ++ export SEEDN=8 ++ SEEDN=8 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 2 --dframe 1B + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_012 ++ SPECDIR=build/specimen_012 ++ mkdir -p build/specimen_012 ++ cd build/specimen_012 +++ echo build/specimen_012 +++ cut -c1-8 +++ md5sum ++ export SEED=54ea9844 ++ SEED=54ea9844 ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012 +++ sed 's/specimen_0*//' ++ export SEEDN=12 ++ SEEDN=12 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/top.py ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 0 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_009 ++ SPECDIR=build/specimen_009 ++ mkdir -p build/specimen_009 ++ cd build/specimen_009 +++ cut -c1-8 +++ md5sum +++ echo build/specimen_009 ++ export SEED=97ca6a42 ++ SEED=97ca6a42 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009 ++ export SEEDN=9 ++ SEEDN=9 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 0 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_008 ++ SPECDIR=build/specimen_008 ++ mkdir -p build/specimen_008 ++ cd build/specimen_008 +++ md5sum +++ echo build/specimen_008 +++ cut -c1-8 ++ export SEED=258dce4a ++ SEED=258dce4a +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008 ++ export SEEDN=8 ++ SEEDN=8 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 0 --dframe 15 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_009 ++ SPECDIR=build/specimen_009 ++ mkdir -p build/specimen_009 ++ cd build/specimen_009 +++ md5sum +++ echo build/specimen_009 +++ cut -c1-8 ++ export SEED=97ca6a42 ++ SEED=97ca6a42 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009 ++ export SEEDN=9 ++ SEEDN=9 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 1B + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_009 ++ SPECDIR=build/specimen_009 ++ mkdir -p build/specimen_009 ++ cd build/specimen_009 +++ md5sum +++ echo build/specimen_009 +++ cut -c1-8 ++ export SEED=97ca6a42 ++ SEED=97ca6a42 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009 ++ export SEEDN=9 ++ SEEDN=9 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 1 --dframe 15 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_009 ++ SPECDIR=build/specimen_009 ++ mkdir -p build/specimen_009 ++ cd build/specimen_009 +++ echo build/specimen_009 +++ md5sum +++ cut -c1-8 ++ export SEED=97ca6a42 ++ SEED=97ca6a42 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009 ++ export SEEDN=9 ++ SEEDN=9 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 1B + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_013 ++ SPECDIR=build/specimen_013 ++ mkdir -p build/specimen_013 ++ cd build/specimen_013 +++ cut -c1-8 +++ md5sum +++ echo build/specimen_013 ++ export SEED=65058682 ++ SEED=65058682 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013 ++ export SEEDN=13 ++ SEEDN=13 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 2 --dframe 1B ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 0 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_009 ++ SPECDIR=build/specimen_009 ++ mkdir -p build/specimen_009 ++ cd build/specimen_009 +++ echo build/specimen_009 +++ cut -c1-8 +++ md5sum ++ export SEED=97ca6a42 ++ SEED=97ca6a42 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009 ++ export SEEDN=9 ++ SEEDN=9 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/top.py + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_009 ++ SPECDIR=build/specimen_009 ++ mkdir -p build/specimen_009 ++ cd build/specimen_009 +++ cut -c1-8 +++ echo build/specimen_009 +++ md5sum ++ export SEED=97ca6a42 ++ SEED=97ca6a42 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009 ++ export SEEDN=9 ++ SEEDN=9 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 0 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_010 ++ SPECDIR=build/specimen_010 ++ mkdir -p build/specimen_010 ++ cd build/specimen_010 +++ echo build/specimen_010 +++ md5sum +++ cut -c1-8 ++ export SEED=2cd8f4a9 ++ SEED=2cd8f4a9 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010 ++ export SEEDN=10 ++ SEEDN=10 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 1B + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_011 ++ SPECDIR=build/specimen_011 ++ mkdir -p build/specimen_011 ++ cd build/specimen_011 +++ cut -c1-8 +++ echo build/specimen_011 +++ md5sum ++ export SEED=e53d240d ++ SEED=e53d240d +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011 ++ export SEEDN=11 ++ SEEDN=11 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 1 --dframe 15 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_010 ++ SPECDIR=build/specimen_010 ++ mkdir -p build/specimen_010 ++ cd build/specimen_010 +++ echo build/specimen_010 +++ md5sum +++ cut -c1-8 ++ export SEED=2cd8f4a9 ++ SEED=2cd8f4a9 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010 ++ export SEEDN=10 ++ SEEDN=10 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 0 --dframe 15 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_010 ++ SPECDIR=build/specimen_010 ++ mkdir -p build/specimen_010 ++ cd build/specimen_010 +++ echo build/specimen_010 +++ md5sum +++ cut -c1-8 ++ export SEED=2cd8f4a9 ++ SEED=2cd8f4a9 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010 ++ export SEEDN=10 ++ SEEDN=10 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 0 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_010 ++ SPECDIR=build/specimen_010 ++ mkdir -p build/specimen_010 ++ cd build/specimen_010 +++ cut -c1-8 +++ echo build/specimen_010 +++ md5sum ++ export SEED=2cd8f4a9 ++ SEED=2cd8f4a9 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010 ++ export SEEDN=10 ++ SEEDN=10 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 1 --dframe 15 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_011 ++ SPECDIR=build/specimen_011 ++ mkdir -p build/specimen_011 ++ cd build/specimen_011 +++ echo build/specimen_011 +++ md5sum +++ cut -c1-8 ++ export SEED=e53d240d ++ SEED=e53d240d +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011 ++ export SEEDN=11 ++ SEEDN=11 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 1 --dframe 15 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_010 ++ SPECDIR=build/specimen_010 ++ mkdir -p build/specimen_010 ++ cd build/specimen_010 +++ md5sum +++ echo build/specimen_010 +++ cut -c1-8 ++ export SEED=2cd8f4a9 ++ SEED=2cd8f4a9 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010 ++ export SEEDN=10 ++ SEEDN=10 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 1 --dframe 15 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_011 ++ SPECDIR=build/specimen_011 ++ mkdir -p build/specimen_011 ++ cd build/specimen_011 +++ echo build/specimen_011 +++ md5sum +++ cut -c1-8 ++ export SEED=e53d240d ++ SEED=e53d240d +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011 ++ export SEEDN=11 ++ SEEDN=11 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 1B + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_014 ++ SPECDIR=build/specimen_014 ++ mkdir -p build/specimen_014 ++ cd build/specimen_014 +++ echo build/specimen_014 +++ cut -c1-8 +++ md5sum ++ export SEED=d825b98b ++ SEED=d825b98b +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014 ++ export SEEDN=14 ++ SEEDN=14 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 0 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_015 ++ SPECDIR=build/specimen_015 ++ mkdir -p build/specimen_015 ++ cd build/specimen_015 +++ echo build/specimen_015 +++ md5sum +++ cut -c1-8 ++ export SEED=e9d05e25 ++ SEED=e9d05e25 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015 ++ export SEEDN=15 ++ SEEDN=15 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/top.py ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 1 --dframe 15 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_010 ++ SPECDIR=build/specimen_010 ++ mkdir -p build/specimen_010 ++ cd build/specimen_010 + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl +++ cut -c1-8 +++ md5sum +++ echo build/specimen_010 ++ export SEED=2cd8f4a9 ++ SEED=2cd8f4a9 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010 ++ export SEEDN=10 ++ SEEDN=10 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 2 --dframe 1B + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_011 ++ SPECDIR=build/specimen_011 ++ mkdir -p build/specimen_011 ++ cd build/specimen_011 +++ md5sum +++ echo build/specimen_011 +++ cut -c1-8 ++ export SEED=e53d240d ++ SEED=e53d240d +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011 ++ export SEEDN=11 ++ SEEDN=11 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 0 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_012 ++ SPECDIR=build/specimen_012 ++ mkdir -p build/specimen_012 ++ cd build/specimen_012 +++ echo build/specimen_012 +++ cut -c1-8 +++ md5sum ++ export SEED=54ea9844 ++ SEED=54ea9844 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012 ++ export SEEDN=12 ++ SEEDN=12 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 0 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_012 ++ SPECDIR=build/specimen_012 ++ mkdir -p build/specimen_012 ++ cd build/specimen_012 +++ md5sum +++ echo build/specimen_012 +++ cut -c1-8 ++ export SEED=54ea9844 ++ SEED=54ea9844 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012 ++ export SEEDN=12 ++ SEEDN=12 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 0 --dframe 15 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_011 ++ SPECDIR=build/specimen_011 ++ mkdir -p build/specimen_011 ++ cd build/specimen_011 +++ echo build/specimen_011 +++ md5sum +++ cut -c1-8 ++ export SEED=e53d240d ++ SEED=e53d240d +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011 ++ export SEEDN=11 ++ SEEDN=11 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 1 --dframe 15 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_012 ++ SPECDIR=build/specimen_012 ++ mkdir -p build/specimen_012 ++ cd build/specimen_012 +++ md5sum +++ echo build/specimen_012 +++ cut -c1-8 ++ export SEED=54ea9844 ++ SEED=54ea9844 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012 ++ export SEEDN=12 ++ SEEDN=12 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 0 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_012 ++ SPECDIR=build/specimen_012 ++ mkdir -p build/specimen_012 ++ cd build/specimen_012 +++ cut -c1-8 +++ echo build/specimen_012 +++ md5sum ++ export SEED=54ea9844 ++ SEED=54ea9844 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012 ++ export SEEDN=12 ++ SEEDN=12 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 2 --dframe 1B + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_011 ++ SPECDIR=build/specimen_011 ++ mkdir -p build/specimen_011 ++ cd build/specimen_011 +++ cut -c1-8 +++ md5sum +++ echo build/specimen_011 ++ export SEED=e53d240d ++ SEED=e53d240d +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011 ++ export SEEDN=11 ++ SEEDN=11 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 0 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_012 ++ SPECDIR=build/specimen_012 ++ mkdir -p build/specimen_012 ++ cd build/specimen_012 +++ echo build/specimen_012 +++ md5sum +++ cut -c1-8 ++ export SEED=54ea9844 ++ SEED=54ea9844 ++++ pwd +++ sed 's/specimen_0*//' +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012 ++ export SEEDN=12 ++ SEEDN=12 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 1 --dframe 15 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_013 ++ SPECDIR=build/specimen_013 ++ mkdir -p build/specimen_013 ++ cd build/specimen_013 +++ echo build/specimen_013 +++ md5sum +++ cut -c1-8 ++ export SEED=65058682 ++ SEED=65058682 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013 ++ export SEEDN=13 ++ SEEDN=13 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 1B + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_013 ++ SPECDIR=build/specimen_013 ++ mkdir -p build/specimen_013 ++ cd build/specimen_013 +++ echo build/specimen_013 +++ cut -c1-8 +++ md5sum ++ export SEED=65058682 ++ SEED=65058682 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013 ++ export SEEDN=13 ++ SEEDN=13 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 1B + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_014 ++ SPECDIR=build/specimen_014 ++ mkdir -p build/specimen_014 ++ cd build/specimen_014 +++ echo build/specimen_014 +++ md5sum +++ cut -c1-8 ++ export SEED=d825b98b ++ SEED=d825b98b +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014 ++ export SEEDN=14 ++ SEEDN=14 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 0 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_012 ++ SPECDIR=build/specimen_012 ++ mkdir -p build/specimen_012 ++ cd build/specimen_012 +++ md5sum +++ echo build/specimen_012 +++ cut -c1-8 ++ export SEED=54ea9844 ++ SEED=54ea9844 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012 ++ export SEEDN=12 ++ SEEDN=12 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 0 --dframe 15 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_013 ++ SPECDIR=build/specimen_013 ++ mkdir -p build/specimen_013 ++ cd build/specimen_013 +++ echo build/specimen_013 +++ cut -c1-8 +++ md5sum ++ export SEED=65058682 ++ SEED=65058682 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013 ++ export SEEDN=13 ++ SEEDN=13 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 1 --dframe 15 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_015 ++ SPECDIR=build/specimen_015 ++ mkdir -p build/specimen_015 ++ cd build/specimen_015 +++ md5sum +++ echo build/specimen_015 +++ cut -c1-8 ++ export SEED=e9d05e25 ++ SEED=e9d05e25 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015 ++ export SEEDN=15 ++ SEEDN=15 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 1 --dframe 15 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_013 ++ SPECDIR=build/specimen_013 ++ mkdir -p build/specimen_013 ++ cd build/specimen_013 +++ cut -c1-8 +++ echo build/specimen_013 +++ md5sum ++ export SEED=65058682 ++ SEED=65058682 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013 ++ export SEEDN=13 ++ SEEDN=13 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 1 --dframe 15 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_014 ++ SPECDIR=build/specimen_014 ++ mkdir -p build/specimen_014 ++ cd build/specimen_014 +++ cut -c1-8 +++ echo build/specimen_014 +++ md5sum ++ export SEED=d825b98b ++ SEED=d825b98b +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014 ++ export SEEDN=14 ++ SEEDN=14 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/top.py ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 1 --dframe 15 + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_016 ++ SPECDIR=build/specimen_016 ++ mkdir -p build/specimen_016 ++ cd build/specimen_016 +++ echo build/specimen_016 +++ md5sum +++ cut -c1-8 ++ export SEED=c8bc5078 ++ SEED=c8bc5078 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016 ++ export SEEDN=16 ++ SEEDN=16 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 2 --dframe 1B + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_017 ++ SPECDIR=build/specimen_017 ++ mkdir -p build/specimen_017 ++ cd build/specimen_017 +++ cut -c1-8 +++ md5sum +++ echo build/specimen_017 ++ export SEED=eccc0d44 ++ SEED=eccc0d44 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017 ++ export SEEDN=17 ++ SEEDN=17 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 2 --dframe 1B + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_018 ++ SPECDIR=build/specimen_018 ++ mkdir -p build/specimen_018 ++ cd build/specimen_018 +++ md5sum +++ echo build/specimen_018 +++ cut -c1-8 ++ export SEED=a651d5f5 ++ SEED=a651d5f5 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018 ++ export SEEDN=18 ++ SEEDN=18 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 1 --dframe 15 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_014 ++ SPECDIR=build/specimen_014 ++ mkdir -p build/specimen_014 ++ cd build/specimen_014 +++ md5sum +++ echo build/specimen_014 +++ cut -c1-8 ++ export SEED=d825b98b ++ SEED=d825b98b +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014 ++ export SEEDN=14 ++ SEEDN=14 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 0 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_019 ++ SPECDIR=build/specimen_019 ++ mkdir -p build/specimen_019 ++ cd build/specimen_019 +++ cut -c1-8 +++ echo build/specimen_019 +++ md5sum ++ export SEED=e5e0e369 ++ SEED=e5e0e369 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019 ++ export SEEDN=19 ++ SEEDN=19 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 0 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_020 ++ SPECDIR=build/specimen_020 ++ mkdir -p build/specimen_020 ++ cd build/specimen_020 +++ md5sum +++ cut -c1-8 +++ echo build/specimen_020 ++ export SEED=c9b71d2c ++ SEED=c9b71d2c +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020 ++ export SEEDN=20 ++ SEEDN=20 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 0 --dframe 15 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_015 ++ SPECDIR=build/specimen_015 ++ mkdir -p build/specimen_015 ++ cd build/specimen_015 +++ echo build/specimen_015 +++ md5sum +++ cut -c1-8 ++ export SEED=e9d05e25 ++ SEED=e9d05e25 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015 ++ export SEEDN=15 ++ SEEDN=15 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/../fuzzaddr/generate.py --oneval 1 --design params.csv --dword 0 --dframe 0 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_015 ++ SPECDIR=build/specimen_015 ++ mkdir -p build/specimen_015 ++ cd build/specimen_015 +++ echo build/specimen_015 +++ cut -c1-8 +++ md5sum ++ export SEED=e9d05e25 ++ SEED=e9d05e25 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015 ++ export SEEDN=15 ++ SEEDN=15 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/../fuzzaddr/generate.py --oneval 0 --design params.csv --dword 0 --dframe 15 + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_016 ++ SPECDIR=build/specimen_016 ++ mkdir -p build/specimen_016 ++ cd build/specimen_016 +++ echo build/specimen_016 +++ md5sum +++ cut -c1-8 ++ export SEED=c8bc5078 ++ SEED=c8bc5078 +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016 ++ export SEEDN=16 ++ SEEDN=16 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl ERROR: [Common 17-49] Internal Data Exception: HDDMProto::writeMessage failed make[3]: *** [build/specimen_015/OK] Error 1 make[3]: *** Waiting for unfinished jobs.... + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_014 ++ SPECDIR=build/specimen_014 ++ mkdir -p build/specimen_014 ++ cd build/specimen_014 +++ echo build/specimen_014 +++ cut -c1-8 +++ md5sum ++ export SEED=d825b98b ++ SEED=d825b98b +++ sed 's/specimen_0*//' ++++ pwd +++ basename /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014 ++ export SEEDN=14 ++ SEEDN=14 + '[' -f /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/top.py ']' + XRAY_DATABASE_ROOT=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/../build/basicdb + python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/top.py + /fast/FPGA/PRJXRAY/prjxray.git/utils/vivado.sh -mode batch -source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl NDup write error: No space left on device NDup write error: No space left on device terminate called after throwing an instance of 'SysAbortEx*' make[3]: *** [build/specimen_015/OK] Error 134 make[3]: *** Waiting for unfinished jobs.... + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_015 ++ SPECDIR=build/specimen_015 ++ mkdir -p build/specimen_015 mkdir: cannot create directory ‘build/specimen_015’: No space left on device make[3]: *** [build/specimen_015/OK] Error 1 make[3]: *** Waiting for unfinished jobs.... + export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int + FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int + source /fast/FPGA/PRJXRAY/prjxray.git/utils/genheader.sh ++ '[' -z zynq7 ']' ++ set -ex ++ export FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int ++ FUZDIR=/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int ++ test 1 -ge 1 ++ test '!' -e '' ++ export SPECDIR=build/specimen_017 ++ SPECDIR=build/specimen_017 ++ mkdir -p build/specimen_017 mkdir: cannot creatmake[3]: *** [build/specimen_016/OK] Error 1 ++ fgrep CRITICAL vivado.log + test -z '' + for x in 'design*.bit' + /fast/FPGA/PRJXRAY/prjxray.git/build/tools/bitread --part_file /fast/FPGA/PRJXRAY/prjxray.git/database/zynq7/xc7z020clg400-1.yaml -F 0x00000000:0xffffffff -o design.bits -z -y design.bit terminate called after throwing an instance of 'std::out_of_range' what(): pos > size() ../fuzzaddr/generate.sh: line 16: 1614 Aborted (core dumped) ${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o ${x}s -z -y $x make[3]: *** [build/specimen_014/OK] Error 134 make[2]: *** [bram_int/build/segbits_tilegrid.tdb] Error 2 NDup write error: No space left on device NDup write error: No space left on device terminate called after throwing an instance of 'SysAbortEx*' make[3]: *** [build/specimen_016/OK] Error 134 Parent process (pid 31528) has died. This helper process will now exit ERROR: [Common 17-1294] Unable to create directory [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/.Xil/Vivado-29078-newhost/dcp0]. make[3]: *** [build/specimen_014/OK] Error 1 ERROR: [Common 17-49] Internal Data Exception: HDDMProto::writeMessage failed make[3]: *** [build/specimen_013/OK] Error 1 ERROR: [Common 17-49] Internal Data Exception: HDDMProto::writeMessage failed make[3]: *** [build/specimen_017/OK] Error 1 ERROR: [Common 17-49] Internal Data Exception: HDDMProto::writeMessage failed make[3]: *** [build/specimen_018/OK] Error 1 NDup write error: No space left on device NDup write error: No space left on device terminate called after throwing an instance of 'SysAbortEx*' make[3]: *** [build/specimen_014/OK] Error 134 make[2]: *** [clb_int/build/segbits_tilegrid.tdb] Error 2 Parent process (pid 789) has died. This helper process will now exit ERROR: [Common 17-1294] Unable to create directory [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/.Xil/Vivado-29234-newhost/dcp0]. make[3]: *** [build/specimen_019/OK] Error 1 make[3]: *** [build/specimen_015/OK] Error 1 make[2]: *** [fifo_int/build/segbits_tilegrid.tdb] Error 2 ERROR: [Common 17-49] Internal Data Exception: HDDMProto::writeMessage failed make[3]: *** [build/specimen_020/OK] Error 1 make[2]: *** [clb/build/segbits_tilegrid.tdb] Error 2 make[1]: *** [run] Error 2