----------------------------------------------------------------------------
--  jtagctrl.vhd
--	JTAG Control Interface
--	Version 1.0
--
--  Copyright (C) 2019 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
----------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;

library machxo2;
use machxo2.components.ALL;


entity top is
    port (
	clk : in std_logic;
	--
	pic_tck : in std_logic;
	pic_tms : in std_logic;
	pic_tdo : in std_logic;
	pic_tdi : out std_logic;
	pic_sig : in std_logic;
	--
	pcie_n : inout std_logic_vector(7 downto 0);
	pcie_s : inout std_logic_vector(7 downto 0);
	--
	led_o : out std_logic_vector(3 downto 0)
    );
end entity top;

architecture RTL of top is

    signal led : std_logic_vector(7 downto 0);

    signal pcie_n_t : std_logic_vector(7 downto 4);
    signal pcie_n_o : std_logic_vector(7 downto 4);
    signal pcie_n_i : std_logic_vector(7 downto 4);

    signal pcie_s_t : std_logic_vector(7 downto 4);
    signal pcie_s_o : std_logic_vector(7 downto 4);
    signal pcie_s_i : std_logic_vector(7 downto 4);

    signal jreg : std_logic_vector(31 downto 0);
    signal jin : std_logic_vector(jreg'range);
    signal jout : std_logic_vector(jreg'range);

    signal jtdi : std_logic;
    signal jtck : std_logic;

    signal jshift : std_logic;
    signal jrstn : std_logic;
    signal jupdate : std_logic;

    signal jce : std_logic_vector(2 downto 1);
    signal jtdo : std_logic_vector(2 downto 1);
    signal jrti : std_logic_vector(2 downto 1);

begin

    GEN_led : for I in led_o'range generate
	OBZ_inst : OBZ
	    port map (
		I => not led(I+4),
		T => led(I),
		O => led_o(I) );
    end generate;

    GEN_pcie : for I in 7 downto 4 generate
	BB_n_inst : BB
	    port map (
		I => pcie_n_o(I),
		T => pcie_n_t(I),
		O => pcie_n_i(I),
		B => pcie_n(I) );

	BB_s_inst : BB
	    port map (
		I => pcie_s_o(I),
		T => pcie_s_t(I),
		O => pcie_s_i(I),
		B => pcie_s(I) );
    end generate;


    JTAGF_inst: JTAGF
	generic map (
	    ER1 => "ENABLED",
	    ER2 => "ENABLED" )
	port map (
	    TCK => '0',
	    TMS => '0',
	    TDI => '0',
	    TDO => open,
	    --
	    JTDI => jtdi,
	    JTCK => jtck,
	    --
	    JSHIFT => jshift,
	    JUPDATE => jupdate,
	    JRSTN => jrstn,
	    --
	    JRTI1 => jrti(1),
	    JRTI2 => jrti(2),
	    --
	    JTDO1 => jtdo(1),
	    JTDO2 => jtdo(2),
	    --
	    JCE1 => jce(1),
	    JCE2 => jce(2) );


/*
    ce1_proc : process(clk, jrti(1))
	variable jce_v : std_logic := '0';
    begin
	if rising_edge(clk) then
	    if jrti(1) = '1' then
		-- jin <= (jin'high => '1', 0 => '1', others => '0');
	    end if;
	end if;
    end process;
*/

    -- jin <= (jin'high => '1', 0 => '1', others => '0');

    er1_proc : process(jtck, jce(1))
    begin
	if falling_edge(jtck) then
	    if jrstn = '0' then		-- Test Logic Reset

	    elsif jce(1) = '1' then	-- Capture/Shift DR
		if jshift = '1' then	-- Shift DR
		    jreg <= jtdi & jreg(jreg'high downto 1);

		else			-- Capture DR
		    jreg <= jin;
		end if;

	    elsif jupdate = '1' then
		jout <= jreg;

	    elsif jrti(1) = '1' then	-- Run Test/Idle

	    else			-- Last Bit
		jreg <= jtdi & jreg(jreg'high downto 1);
	    end if; 
	end if;
    end process;

    jtdo(1) <= jreg(0);

    pcie_n(0) <= pic_tms when jout(16) else 'Z';
    pcie_n(1) <= pic_tck when jout(16) else 'Z';
    pcie_n(2) <= pic_tdo when jout(16) else 'Z';

    pcie_s(0) <= pic_tms when jout(17) else 'Z';
    pcie_s(1) <= pic_tck when jout(17) else 'Z';
    pcie_s(2) <= pic_tdo when jout(17) else 'Z';

    pic_tdi <= pcie_n(3) when jout(18) else pcie_s(3);

    -- jin(7 downto 0) <= pcie_n(7 downto 0);
    -- jin(15 downto 8) <= pcie_s(7 downto 0);

    jin(7 downto 4) <= pcie_n_i(7 downto 4);
    jin(15 downto 12) <= pcie_s_i(7 downto 4);

    pcie_n_o(7 downto 4) <= jout(7 downto 4);
    pcie_n_t(7 downto 4) <= not jout(3 downto 0);

    pcie_s_o(7 downto 4) <= jout(15 downto 12);
    pcie_s_t(7 downto 4) <= not jout(11 downto 8);

    led <= x"0" & pcie_n_i(7 downto 4) when jout(20) else
	   x"0" & pcie_s_i(7 downto 4) when jout(21) else
           jout(31 downto 24);

/*
    dbg_proc : process(clk)
	variable cnt_v : unsigned(15 downto 0) := (others => '0');
    begin
	if rising_edge(clk) then
	    cnt_v := cnt_v + "1";
	    pic_tck <= cnt_v(15);
	    pic_tdo <= cnt_v(14);
	    pic_sig <= cnt_v(13);
	    pic_tms <= cnt_v(12);
	    pic_tdi <= cnt_v(11);
	end if;
    end process;
*/

end RTL;