library IEEE; use IEEE.std_logic_1164.ALL; use IEEE.numeric_std.ALL; entity top is port ( pclk : in std_logic; -- south : out std_logic_vector (7 downto 0); north : out std_logic_vector (7 downto 0) ); end entity top; architecture RTL of top is begin count_proc : process(pclk) variable bcnt_v : unsigned (31 downto 0); begin if rising_edge(pclk) then -- clk bcnt_v := bcnt_v + 1; end if; south <= std_logic_vector(bcnt_v(23 downto 16)); north <= std_logic_vector(bcnt_v(31 downto 24)); end process; end RTL;