//  MAIN_test.c

/*  Copyright (C) 2016 H.Poetzl
**	
**  This program is free software: you can redistribute it and/or
**  modify it under the terms of the GNU General Public License
**  as published by the Free Software Foundation, either version
**  2 of the License, or (at your option) any later version.
**
**  PB0 ... AT_#SS
**  PB1 ... AT_SCK
**  PB2 ... AT_MOSI
**  PB3 ... AT_MISO
**  PB4 ... AT_PB4
**  PB5 ... AT_PB5
**  PB6 ... AT_#RTSPD
**  PB7 ... AT_SEL
**
**  PC0 ... AT_PIO0
**  PC1 ... AT_PIO1
**  PC2 ... AT_PIO2
**  PC3 ... AT_PIO3
**  PC4 ... AT_PIO4
**  PC5 ... AT_PIO5
**  PC6 ... AT_PIO6
**  PC7 ... AT_PIO7
**
**  PD0 ... AT_SCL
**  PD1 ... AT_SDA
**
**  PD2 ... AT_RXD1
**  PD3 ... AT_TXD1
**
**  PD5 ... AT_TXCAN
**  PD6 ... AT_RXCAN
**
**  PE0 ... AT_RXD0
**  PE1 ... AT_TXD0
**
**  PE2 ... AT_#STBY
**
**  PE3 ... AT_LEDA
**  PE4 ... AT_LEDB
**  PE5 ... AT_LEDC
**
**  PE6 ... AT_LVL_EN
**  PE7 ... AT_INT7
**
**  PF0 ... AT_LED0
**  PF1 ... AT_LED1
**  PF2 ... AT_LED2
**  PF3 ... AT_LED3
**
**  PG0 ... AT_CFG
*/

#define CAN_PWR

#define F_CPU 16000000 

#include <avr/io.h>
#include <avr/interrupt.h>
#include <avr/sleep.h>
#include <avr/wdt.h>
#include <util/delay.h>
#include <stdint.h>
#include <stdbool.h>



#define PN532_RELAX 1000

#define PN532_STATUS		0x02
#define PN532_WRITE		0x01
#define PN532_READ		0x03
#define PN532_READY		0x01

#define PN532_PREAMBLE		0x00
#define PN532_SCODE1		0x00
#define PN532_SCODE2		0xFF
#define PN532_POSTAMBLE		0x00

#define PN532_HTOPN532		0xD4

#define PN532_CC_DIAGNOSE	0x00
#define PN532_CC_VERSION	0x02
#define PN532_CC_GENSTAT	0x04
#define PN532_CC_READREG	0x06
#define PN532_CC_WRITEREG	0x08

#define PN532_CC_READGPIO	0x0C
#define PN532_CC_WRITEGPIO	0x0E

#define PN532_CC_BAUDRATE	0x10
#define PN532_CC_SETPARAM	0x12
#define PN532_CC_SAMCONFIG	0x14
#define PN532_CC_POWERDOWN	0x16

#define PN532_CC_RFCONFIG	0x32
#define PN532_CC_RFREGTEST	0x58

#define PN532_CC_PASSIVE	0x4A
#define PN532_CC_AUTOPOLL	0x60


#define RFCI_FIELD		0x01	/*  1 */
#define RFCI_TIMING		0x02	/*  3 */
#define RFCI_RETRY_DATA		0x04	/*  1 */
#define RFCI_RETRY_SELECT	0x05	/*  3 */
#define RFCI_TYPE_A_106		0x0A	/* 11 */
#define RFCI_TYPE_A_212_424	0x0B	/*  8 */
#define RFCI_TYPE_B		0x0C	/*  3 */
#define RFCI_TYPE_14443_4	0x0D	/*  9 */


#define LED_A	(1 << 3)
#define LED_B	(1 << 4)
#define LED_C	(1 << 5)


uint8_t buf[256];

uint64_t cycle = 0;
uint8_t col = ~0;

static uint8_t gpin[7] = { 0 };
static uint8_t gddr[7] = { 0 };
static uint8_t gport[7] = { 0 };
static uint8_t gmask[7] = { ~0, 0x80, ~0, ~0, 0x2C, ~0, ~0 };

static uint8_t mask[7];
static uint8_t tcnt[7][8] = {{ 0 }};

static const uint8_t msg_ff[] =
	{ 0xFF, 0xFF, 0xFF, 0xFF };
static const uint8_t msg_aa[] =
	{ 0xAA, 0xAA, 0xAA, 0xAA };
static const uint8_t msg_ok[] =
	{ 0x00, 0x00, 0xFF, 0x00, 0xFF, 0x00 };
static const uint8_t msg_ver[] = 
	{ 0x00, 0x00, 0xFF, 0x06, 0xFA, 0xD5, 0x03, 0x32,
	  0x01, 0x06, 0x07, 0xE8, 0x00 };

static const uint8_t msg_nc[] =
	{ 0x00, 0x00, 0xFF, 0x03, 0xFD, 0xD5, 0x4B, 
	  0x00, 0xE0, 0x00 };
static const uint8_t msg_card1[] =
	{ 0x00, 0x00, 0xFF, 0x0F, 0xF1, 0xD5, 0x4B,
	  0x01, 0x01, 0x03, 0x44, 0x20, 0x07, 0x04,
	  0x4E, 0x08, 0x32, 0x50, 0x38, 0x80, 0xDC, 0x00 };
static const uint8_t msg_card2[] =
	{ 0x00, 0x00, 0xFF, 0x0F, 0xF1, 0xD5, 0x4B,
	  0x01, 0x01, 0x03, 0x44, 0x20, 0x07, 0x04,
	  0x70, 0x94, 0x3A, 0x50, 0x38, 0x80, 0x26, 0x00 };
static const uint8_t msg_card3[] =
	{ 0x00, 0x00, 0xFF, 0x0C, 0xF4, 0xD5, 0x4B,
	  0x01, 0x01, 0x00, 0x04, 0x08, 0x04, 0xEB,
	  0xE9, 0xDD, 0x0B, 0x12, 0x00 };




static inline
void uart0_tx(char chr)
{
    while (!(UCSR0A & (1<<UDRE0)));
    UDR0 = chr;
    col++;
}

static inline
void uart0_tx_hex(uint8_t val)
{
    char chr = '0' + (val & 0xF);

    if (chr > '9')
	chr += 'A' - '9' - 1;
    uart0_tx(chr);
}

static inline
void uart0_tx_byte(uint8_t val)
{
    uart0_tx_hex(val >> 4);
    uart0_tx_hex(val & 0xF);
}

static inline
void uart0_tx_uint16(uint16_t val)
{
    uart0_tx_byte(val >> 8);
    uart0_tx_byte(val & 0xFF);
}

static inline
void uart0_tx_uint32(uint32_t val)
{
    uart0_tx_uint16(val >> 16);
    uart0_tx_uint16(val & 0xFFFF);
}

static inline
void uart0_tx_uint64(uint64_t val)
{
    uart0_tx_uint32(val >> 32L);
    uart0_tx_uint32(val & 0xFFFFFFFFL);
}

static inline
void uart0_tx_newline(void)
{
    if (col) {
	uart0_tx('\r');
	uart0_tx('\n');
	col = 0;
    }
}

static
void uart0_tx_dump(const uint8_t *buf, uint8_t len)
{
    uint8_t cnt;

    uart0_tx('\t');
    for (cnt = 0; cnt < len; cnt++) {
	uart0_tx_byte(buf[cnt]);
	if (cnt != len - 1)
	    uart0_tx('.');
    }
}



static inline
uint8_t spidata(uint8_t val)
{
    SPDR = val;
    while (!(SPSR & (1<<SPIF)));
    return SPDR;
}


static inline
uint8_t pn532_status(void)
{
    uint8_t val;

    PORTB &= ~1;				// #SS low
    _delay_us(PN532_RELAX);
    spidata(PN532_STATUS);
    val = spidata(0);
    PORTB |= 1;					// #SS high
    return val;
}

static inline
uint8_t pn532_wait(uint16_t timeout)
{
    for (; timeout ; timeout--) {
	uint8_t stat = pn532_status();
	if (stat & PN532_READY)
	    break;
    }
    return timeout;
}

static inline
uint8_t pn532_read(uint8_t *buf, uint8_t len)
{
    uint8_t cnt = 0;

    if (len) {
	PORTB &= ~1;				// #SS low
	_delay_us(PN532_RELAX);
	spidata(PN532_READ);
	cnt = len;
	while (len--)
	    *buf++ = spidata(0);
	PORTB |= 1;				// #SS high
    } else {
	len = 5;

	PORTB &= ~1;			    // #SS low
	_delay_us(PN532_RELAX);
	spidata(PN532_READ);
	for (cnt=0; cnt < len; cnt++) {
	    *buf++ = spidata(0);
	    if (cnt == 3) {
		len = buf[-1] + 7;
	    } else if (cnt == 4) {
		uint8_t chk = buf[-1] + buf[-2];

		if (chk == 0xFF)
		    len = 6;
		else if (chk != 0)
		    break;
	    }
	}
	PORTB |= 1;			    // #SS high
    }
    return cnt;
}


static inline
uint8_t pn532_pkg(uint8_t *buf, uint8_t *dat, uint8_t len)
{
    uint8_t sum = 0;
    uint8_t cnt = len;
    uint8_t *ptr = buf;

    len++;
    *ptr++ = PN532_PREAMBLE;
    sum += PN532_PREAMBLE;
    *ptr++ = PN532_SCODE1;
    sum += PN532_SCODE1;
    *ptr++ = PN532_SCODE2;
    sum += PN532_SCODE2;
    *ptr++ = len;
    *ptr++ = (~len + 1);
    *ptr++ = PN532_HTOPN532;
    sum += PN532_HTOPN532;
    while (cnt--) {
	*ptr++ = *dat;
	sum += *dat++;
    }
    *ptr++ = (~sum);
    *ptr++ = PN532_POSTAMBLE;
    return (ptr - buf);
}

static inline
void pn532_write(uint8_t *dat, uint8_t len, uint8_t dump)
{
    uint8_t buf[256];
    uint8_t cnt;
    uint8_t *ptr = buf;

    cnt = pn532_pkg(buf, dat, len);
    if (dump) {
	uart0_tx_newline();
	uart0_tx('[');
	uart0_tx_byte(cnt);
	uart0_tx(']');
	uart0_tx_dump(buf, cnt);
    }

    PORTB &= ~1;				// #SS low
    _delay_us(PN532_RELAX);
    spidata(PN532_WRITE);
    while (cnt--)
	spidata(*ptr++);
    PORTB |= 1;					// #SS high
}



static inline
void check(uint8_t idx, uint8_t pin, uint8_t ddr, uint8_t port)
{
    uint8_t xor = pin ^ gpin[idx];
    uint8_t msk = mask[idx];

    if (xor & msk) {
	for (uint8_t bit=0; bit<8; bit++) {
	    if (((xor & msk) >> bit) & 1) {
		if (tcnt[idx][bit] < 15) {
		    uart0_tx('A' + idx);
		    uart0_tx_hex(bit);
		    if ((pin >> bit) & 1)
			uart0_tx('+');
		    else
			uart0_tx('-');
		    tcnt[idx][bit]++;
		} else if (tcnt[idx][bit] != 0xFF) {
		    uart0_tx('A' + idx);
		    uart0_tx_hex(bit);
		    uart0_tx('!');
		    mask[idx] &= ~(1 << bit);
		    tcnt[idx][bit] = 0xFF;
		}
	    }
	}
	gpin[idx] = pin;
    }

    if ((msk ^ mask[idx]) || 
	((ddr ^ gddr[idx]) & gmask[idx]) || 
	((port ^ gport[idx]) & gmask[idx])) {

	uart0_tx_newline();
	uart0_tx('A' + idx);
	uart0_tx(':');
	uart0_tx(' ');
	uart0_tx_byte(pin);
	uart0_tx('/');
	uart0_tx_byte(ddr);
	uart0_tx('/');
	uart0_tx_byte(port);
	uart0_tx('|');
	uart0_tx_byte(mask[idx]);
	uart0_tx(' ');
	uart0_tx('#');
	uart0_tx_uint64(cycle);
	uart0_tx_newline();

	gddr[idx] = ddr;
	gport[idx] = port;
    }
}



static inline
void test_adc(uint8_t prev, uint8_t this)
{
    uint8_t val = ADCH;

    if (val >= 0xF8) {
	uart0_tx('.');
    } else {
	uart0_tx('&');
	uart0_tx_hex(prev & 0x7);
	uart0_tx('=');
	uart0_tx_byte(val);
    }

    ADMUX = (ADMUX & ~0xF) | (this & 0x7);
    ADCSRA |= (1 << ADSC);		// start acquisition
}


static inline
uint8_t msg_cmp(const uint8_t *msg, uint8_t len)
{
    uint8_t i;
    for (i=0; i<len; i++)
	if (buf[i] != msg[i])
	    return 0;
    return 1;
}

static inline
uint8_t check_msg(const uint8_t *msg, uint8_t cnt)
{
    uint8_t len, log = 0;

    len = pn532_read(buf, 0);

    if ((len != cnt) ||
	!msg_cmp(msg, cnt))
	log = 1;

    if (len && log) {
	uart0_tx_dump(buf, len);
	uart0_tx('|');
	uart0_tx_dump(msg, cnt);
	uart0_tx_newline();
    }
    return len;
}

static inline
void test_pn532(uint8_t prev)
{
    uint8_t active = (prev >> 4) & 1;

    buf[0] = PN532_CC_VERSION;
    pn532_write(buf, 1, 0);
		
    if (active) {
	if (!check_msg(msg_ok, sizeof(msg_ok)))
	    uart0_tx('!');
	if (!check_msg(msg_ver, sizeof(msg_ver)))
	    uart0_tx('!');
    } else {
	check_msg(msg_ff, sizeof(msg_ff));
    }
}




ISR (BADISR_vect)
{
    uart0_tx('$');
    asm("jmp 0");
}

void bad_pc(void)
{
    uart0_tx('%');
    asm("jmp 0");
}



int check_btn(void)
{
    return (!(PING & 1));
}

void check_loop(void)
{
    uint8_t prev = 0;

    DDRE = 0x40;		// EN output
    PORTE = ~0x00;		// EN = 1
    PORTB = ~0x40;		// !RTSPD = 0

    _delay_ms(100);

    while (1) {
	check(0, PINA, DDRA, PORTA);
	check(1, PINB, DDRB, PORTB);
	check(2, PINC, DDRC, PORTC);
	check(3, PIND, DDRD, PORTD);
	check(4, PINE, DDRE, PORTE);
	check(5, PINF, DDRF, PORTF);
	check(6, PING, DDRG, PORTG);

	cycle++;	
	
	if (check_btn())
	    return;
	
	uint8_t this = (cycle >> 10) & 0xFF;

	if (this ^ prev) {
	    test_adc(prev, this);
	    test_pn532(prev);

	    if (!(this & 0xF)) {
		uart0_tx_newline();
		uart0_tx('#');
		uart0_tx_uint64(cycle);
		uart0_tx_newline();
	    }

	    switch ((this >> 4) & 3) {
	    case 0:			// reset PN532
		DDRE = 0x40;		// EN output
		PORTB = ~0x40;		// !RTSPD = 0
		break;
	    case 1:			// activate PN532
		PORTB = ~0x00;		// !RTSPD = 1
		_delay_ms(100);
		break;
	    case 2:			// reset PN532
		DDRE = 0x00;		// all input
		PORTB = ~0x40;		// !RTSPD = 0
		break;
	    case 3:			//
		PORTB = ~0x00;		// !RTSPD = 1
		_delay_ms(100);
		break;
	    }


	#ifdef CAN_PWR
	    PORTC = (PORTC & ~0xC) |	// power modes
		((this >> 4) & 0xC);
	#endif
	    prev = this;
	}
    }
}


void init_adc(void)
{
    ADMUX = 0;				// start with ADC0
    ADMUX |= (1 << REFS0);		// VCC as reference
    ADMUX |= (1 << ADLAR);		// left align
    ADCSRA = (7 << ADPS0);		// 1:128 prescaler
    ADCSRB = (0 << ADTS0);		// free running
    ADCSRA |= (1 << ADEN);		// enable ADC
    ADCSRA |= (1 << ADSC);		// start acquisition
}

void init_spi(void)
{
    SPCR = (1<<MSTR)|(0<<SPR0)|(1<<SPE)|(1<<DORD);

    DDRB = 0x47;			// #RTSPD, MOSI, SCK, #SS
    PORTB = 0xFF;			// all pullup
}

void init_usart(void)
{
    UBRR0L = 52;			// 38400 @ 16MHz
    UBRR0L = 16;			// 115200 @ 16MHz
    UBRR0L = 3;				// 500k @ 16MHz

    UCSR0A = (1<<U2X0);			// 2x mode
    UCSR0B = (1<<RXEN0)|(1<<TXEN0);	// enable
    UCSR0C = (3<<UCSZ00);		// 8-bit
}

void init_leds(void)
{
    DDRE = 0x38;			// LVL_EN
    PORTE = 0xFF;			// all pullup
}

void init_pn532(void)
{
    uint8_t len;


/*  buf[0] = PN532_CC_VERSION;
    pn532_write(buf, 1, 0);
		
    check_msg(msg_ok, sizeof(msg_ok));
    check_msg(msg_ver, sizeof(msg_ver)); */

    buf[0] = PN532_CC_SAMCONFIG;
    buf[1] = 0x01;
    pn532_write(buf, 2, 0);
    pn532_wait(10);
    check_msg(msg_ok, sizeof(msg_ok));

    buf[0] = PN532_CC_SETPARAM;
    buf[1] = 0x14;
    pn532_write(buf, 2, 0);
    pn532_wait(10);
    check_msg(msg_ok, sizeof(msg_ok));

    buf[0] = PN532_CC_SETPARAM;
    buf[1] = 0x24;			// Disable auto RATS
    pn532_write(buf, 2, 0);
    pn532_wait(10);
    check_msg(msg_ok, sizeof(msg_ok));

    buf[0] = PN532_CC_WRITEREG;
    buf[1] = 0x63; buf[2] = 0x02; buf[3] = 0x80;	// CIU_TxMode
    buf[4] = 0x63; buf[5] = 0x03; buf[7] = 0x80;	// CIU_RxMode
    pn532_write(buf, 7, 0);
    pn532_wait(10);
    check_msg(msg_ok, sizeof(msg_ok));

    buf[0] = PN532_CC_WRITEREG;
    buf[1] = 0x63; buf[2] = 0x05; buf[3] = 0xC0;	// CIU_TxAuto
    buf[4] = 0x63; buf[5] = 0x3C; buf[6] = 0x10;	// CIU_Control
    pn532_write(buf, 7, 0);
    pn532_wait(10);
    check_msg(msg_ok, sizeof(msg_ok));

    buf[0] = PN532_CC_RFCONFIG;
    buf[1] = RFCI_RETRY_SELECT;
    // buf[2] = 0xFF; buf[3] = 0xFF; buf[4] = 0xFF;
    buf[2] = 0x00; buf[3] = 0x00; buf[4] = 0x00;
    pn532_write(buf, 5, 0);
    pn532_wait(10);
    check_msg(msg_ok, sizeof(msg_ok));

/*  Not required for check
    uart0_tx('w');
    buf[0] = PN532_CC_RFCONFIG;
    buf[1] = RFCI_FIELD;
    buf[2] = 0x01;			// enable Field
    pn532_write(buf, 3, 0);
    pn532_wait(10);
    check_msg(msg_ok, sizeof(msg_ok));
*/

/*  Not required to detect card
    buf[0] = PN532_CC_AUTOPOLL;
    buf[1] = 0x14; buf[2] = 0x02; buf[3] = 0x20;
    buf[4] = 0x10; buf[5] = 0x03; buf[6] = 0x11;
    buf[7] = 0x12; buf[8] = 0x04;
    pn532_write(buf, 9, 0);
*/

    PORTE &= ~LED_B;

    buf[0] = PN532_CC_PASSIVE;
    buf[1] = 0x01; buf[2] = 0x00;
    pn532_write(buf, 3, 0);
    pn532_wait(10);
    check_msg(msg_ok, sizeof(msg_ok));

    if (!pn532_wait(25))
	uart0_tx('?');

    len = pn532_read(buf, 0);

    PORTB = ~0x40;	// !RTSPD = 0
    PORTE |= LED_B;

    if (len == sizeof(msg_nc) &&
	msg_cmp(msg_nc, len)) {
	uart0_tx('N');
    } else if (len == sizeof(msg_card1) &&
	msg_cmp(msg_card1, len)) {
	uart0_tx('X');
	PORTE &= ~LED_A;
	_delay_ms(250);
    } else if (len == sizeof(msg_card2) &&
	msg_cmp(msg_card2, len)) {
	uart0_tx('Y');
	PORTE &= ~LED_C;
	_delay_ms(250);
    } else if (len == sizeof(msg_card3) &&
	msg_cmp(msg_card3, len)) {
	uart0_tx('Z');
	wdt_disable();
    } else {
	uart0_tx_dump(buf, len);
	uart0_tx_newline();
    }
}


void shut_down(void)
{
    ADCSRA &= ~(1 << ADEN);		// disable ADC
    SPCR &= ~(1<<SPE);			// disbale SPI
    UCSR0B = 0;				// disable USART
    MCUCR = 0x90;			// JTD and PUD

    DDRE = 0x40;		// EN output
    PORTB = ~0x40;		// !RTSPD = 0

    set_sleep_mode(SLEEP_MODE_PWR_DOWN);
    sleep_mode();
}

int main(void)
{
    uint8_t res = MCUSR;
    uint8_t opt = 0;

    MCUSR = 0;
    MCUCR = 0x80;

    cli();

    if (res & 0x8) {		// watchdog
	if (!check_btn()) {
	    init_usart();
	    init_spi();
	    init_leds();
	    uart0_tx('^');
	    wdt_enable(WDTO_500MS);
	    init_pn532();
	    uart0_tx_newline();
	    _delay_ms(5);
	    shut_down();
	}
    }


    DDRA = 0x00;			// all in
    PORTA = 0xFF;			// all pullup

    DDRB = 0x47;			// #RTSPD, MOSI, SCK, #SS
    PORTB = 0xFF;			// all pullup

    DDRC = 0x00;			// all in
    PORTC = 0xFF;			// all pullup

    DDRD = 0x00;			// all in
    PORTD = 0xFF;			// all pullup

    DDRE = 0x40;			// LVL_EN
    PORTE = 0xFF;			// all pullup

    DDRF = 0x00;			// all in
    PORTF = 0xFF;			// all pullup

    DDRG = 0x00;			// all in
    PORTG = 0xFF;			// all pullup


#ifdef CAN_PWR
    DDRC = 0x0C;			// GPIO2/3 out
    gmask[2] &= ~0x0C;			// mask out
#endif

    init_usart();

    _delay_ms(100);

    uart0_tx_newline();
    uart0_tx('@');
    uart0_tx_byte(res);
    uart0_tx_newline();

    uart0_tx('#');
    uart0_tx_uint64(0x123456789ABCDEF0);
    uart0_tx('-');
    uart0_tx_byte(0x04);
    uart0_tx_newline();

    _delay_ms(100);

    init_adc();
    init_spi();

    for (uint8_t i = 0; i<7; i++)
	mask[i] = gmask[i];

    check_loop();
    opt = check_btn();
    uart0_tx('~');
    uart0_tx_byte(opt);

    wdt_enable(WDTO_2S);
    shut_down();

    uart0_tx('*');
    while (1); 
}