---------------------------------------------------------------------------- -- top.vhd -- ZYBO simple HDMI example -- Version 1.1 -- -- Copyright (C) 2014 H.Poetzl -- -- This program is free software: you can redistribute it and/or -- modify it under the terms of the GNU General Public License -- as published by the Free Software Foundation, either version -- 2 of the License, or (at your option) any later version. -- -- Vivado 2013.4: -- mkdir -p build.vivado -- (cd build.vivado && vivado -mode tcl -source ../vivado.tcl) ---------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.ALL; library unisim; use unisim.VCOMPONENTS.ALL; use work.vect_pkg.ALL; entity top is port ( clk_125 : in std_logic; -- sw : in std_logic_vector (3 downto 0); led : out std_logic_vector (3 downto 0); -- vga_r : out std_logic_vector (4 downto 0); vga_g : out std_logic_vector (5 downto 0); vga_b : out std_logic_vector (4 downto 0); -- vga_hs : out std_logic; vga_vs : out std_logic; -- hdmi_clk_p : out std_logic; hdmi_clk_n : out std_logic; -- hdmi_d_p : out std_logic_vector (2 downto 0); hdmi_d_n : out std_logic_vector (2 downto 0); -- hdmi_hpd : in std_logic; hdmi_cec : in std_logic; -- hdmi_scl : inout std_logic; hdmi_sda : inout std_logic; -- hdmi_out_en : out std_logic ); end entity top; architecture RTL of top is signal tmds : std_logic_vector (3 downto 0); signal pll_fbout : std_logic; signal pll_fbin : std_logic; signal pll_locked : std_logic; signal pll_pwrdwn : std_logic; signal pll_reset : std_logic; signal pll_pix_clk : std_logic; signal pll_bit_clk : std_logic; signal pll_bit_clk_n : std_logic; signal pix_clk : std_logic; signal bit_clk : std_logic; signal bit_clk_n : std_logic; signal scan_clk : std_logic; signal scan_reset : std_logic; signal scan_blank : std_logic; signal scan_hsync : std_logic; signal scan_vsync : std_logic; signal scan_hpos : std_logic_vector (11 downto 0); signal scan_vpos : std_logic_vector (11 downto 0); signal scan_frame : std_logic; signal rng_clk : std_logic; signal rng_ce : std_logic; signal rng_mode : std_logic; signal rng_s_in : std_logic; signal rng0_s_out : std_logic; signal rng0_data : std_logic_vector (31 downto 0); signal rng1_s_out : std_logic; signal rng1_data : std_logic_vector (31 downto 0); signal rng2_s_out : std_logic; signal rng2_data : std_logic_vector (31 downto 0); signal rng3_s_out : std_logic; signal rng3_data : std_logic_vector (31 downto 0); signal rgb_data : vec8_a (2 downto 0) := (others => (others => '0')); signal rgb_de : std_logic; signal rgb_blank : std_logic; signal rgb_hsync : std_logic; signal rgb_vsync : std_logic; signal dvid_enable : std_logic; signal dvid_reset : std_logic; begin hdmi_out_en <= sw(3); hdmi_scl <= 'Z'; hdmi_sda <= 'Z'; mmcm_inst : MMCME2_BASE generic map ( BANDWIDTH => "LOW", CLKIN1_PERIOD => 8.0, -- CLKFBOUT_MULT_F => 11.88, CLKFBOUT_PHASE => 0.000, -- CLKOUT0_DIVIDE_F => 5.0, CLKOUT1_DIVIDE => 1, CLKOUT2_DIVIDE => 1, -- CLKOUT0_PHASE => 0.000, CLKOUT1_PHASE => 0.000, CLKOUT2_PHASE => 180.000, -- DIVCLK_DIVIDE => 2 ) port map ( CLKIN1 => clk_125, CLKFBOUT => pll_fbout, CLKFBIN => pll_fbin, CLKOUT0 => pll_pix_clk, CLKOUT1 => pll_bit_clk, CLKOUT2 => pll_bit_clk_n, LOCKED => pll_locked, PWRDWN => pll_pwrdwn, RST => pll_reset ); pll_fbin <= pll_fbout; pll_pwrdwn <= '0'; pll_reset <= '0'; BUFG_bit_clk_inst : BUFG port map ( I => pll_bit_clk, -- 1-bit input: Clock buffer input O => bit_clk ); -- 1-bit output: Clock output port BUFG_bit_clk_n_inst : BUFG port map ( I => pll_bit_clk_n, -- 1-bit input: Clock buffer input O => bit_clk_n ); -- 1-bit output: Clock output port BUFG_pix_clk_inst : BUFG port map ( I => pll_pix_clk, -- 1-bit input: Clock buffer input O => pix_clk ); -- 1-bit output: Clock output port scan_vga_inst : entity work.scan_vga port map ( clk => scan_clk, reset => scan_reset, -- total_w => x"897", total_h => x"464", -- hdisp_s => x"000", hdisp_e => x"780", vdisp_s => x"000", vdisp_e => x"438", -- hsync_s => x"7DC", hsync_e => x"814", vsync_s => x"43A", vsync_e => x"440", -- blank => scan_blank, hsync => scan_hsync, vsync => scan_vsync, -- hpos => scan_hpos, vpos => scan_vpos, frame => scan_frame); scan_clk <= pix_clk; scan_reset <= '0'; prng_inst0 : entity work.prng32 (LUT_SR) port map ( clk => rng_clk, ce => rng_ce, mode => rng_mode, s_in => rng_s_in, s_out => rng0_s_out, rng => rng0_data ); prng_inst1 : entity work.prng32 (LFSR_FIB) port map ( clk => rng_clk, ce => rng_ce, mode => rng_mode, s_in => rng_s_in, s_out => rng1_s_out, rng => rng1_data ); prng_inst2 : entity work.prng32 (LFSR_GAL) port map ( clk => rng_clk, ce => rng_ce, mode => rng_mode, s_in => rng_s_in, s_out => rng2_s_out, rng => rng2_data ); prng_inst3 : entity work.prng32 (MT32) port map ( clk => rng_clk, ce => rng_ce, mode => rng_mode, s_in => rng_s_in, s_out => rng3_s_out, rng => rng3_data ); rng_clk <= pix_clk; rng_ce <= not scan_blank; rng_mode <= '0'; rng_s_in <= '1'; rgb_proc : process (scan_clk) begin if rising_edge(scan_clk) then if scan_hpos = x"000" or scan_vpos = x"000" or scan_hpos = x"77F" or scan_vpos = x"437" then rgb_data(0) <= x"FFF"; rgb_data(1) <= x"FFF"; rgb_data(2) <= x"FFF"; elsif scan_hpos < x"280" then rgb_data(0) <= rng0_data(7 downto 0); rgb_data(1) <= rng0_data(15 downto 8); rgb_data(2) <= rng0_data(23 downto 16); elsif scan_hpos < x"500" then if scan_vpos < x"100" then rgb_data(0) <= rng1_data(7 downto 0); rgb_data(1) <= rng1_data(15 downto 8); rgb_data(2) <= rng1_data(23 downto 16); elsif scan_vpos < x"200" then rgb_data(0) <= rng2_data(7 downto 0); rgb_data(1) <= rng2_data(15 downto 8); rgb_data(2) <= rng2_data(23 downto 16); else rgb_data(0) <= rng1_data(7 downto 0) xor rng2_data(7 downto 0); rgb_data(1) <= rng1_data(15 downto 8) xor rng2_data(15 downto 8); rgb_data(2) <= rng1_data(23 downto 16) xor rng2_data(23 downto 16); end if; elsif scan_hpos < x"780" then rgb_data(0) <= rng3_data(7 downto 0); rgb_data(1) <= rng3_data(15 downto 8); rgb_data(2) <= rng3_data(23 downto 16); else rgb_data(0) <= x"000"; rgb_data(1) <= x"000"; rgb_data(2) <= x"000"; end if; rgb_vsync <= scan_vsync; rgb_hsync <= scan_hsync; rgb_blank <= scan_blank; rgb_de <= not scan_blank; end if; end process; vga_sync_proc : process (scan_clk) begin if rising_edge(scan_clk) then if sw(2) = '1' then vga_hs <= rgb_hsync xor sw(0); vga_vs <= rgb_vsync xor sw(1); else vga_hs <= sw(0); vga_vs <= sw(1); end if; end if; end process; vga_data_proc : process (scan_clk) begin if rising_edge(scan_clk) then if rgb_blank = '0' and sw(2) = '1' then vga_r <= rgb_data(0)(7 downto 3); vga_g <= rgb_data(1)(7 downto 2); vga_b <= rgb_data(2)(7 downto 3); else vga_r <= (others => '0'); vga_g <= (others => '0'); vga_b <= (others => '0'); end if; end if; end process; div_led_inst0 : entity work.async_div generic map ( STAGES => 28 ) port map ( clk_in => bit_clk, clk_out => led(0) ); div_led_inst1 : entity work.async_div generic map ( STAGES => 28 ) port map ( clk_in => pix_clk, clk_out => led(1) ); led(2) <= scan_hsync; led(3) <= scan_vsync; OBUFDS_clk_inst : OBUFDS generic map ( IOSTANDARD => "TMDS_33", SLEW => "SLOW" ) port map ( O => hdmi_clk_p, OB => hdmi_clk_n, I => tmds(3) ); OBUFDS_GEN: for I in 2 downto 0 generate OBUFDS_data_inst : OBUFDS generic map ( IOSTANDARD => "TMDS_33", SLEW => "SLOW" ) port map ( O => hdmi_d_p(I), OB => hdmi_d_n(I), I => tmds(2 - I) ); end generate; rgb_dvid_inst : entity work.rgb_dvid port map ( pix_clk => pix_clk, bit_clk => bit_clk, bit_clk_n => bit_clk_n, -- enable => dvid_enable, reset => dvid_reset, -- rgb => rgb_data, -- de => rgb_de, hsync => rgb_hsync, vsync => rgb_vsync, -- tmds => tmds ); dvid_reset <= not sw(3); dvid_enable <= sw(3); end RTL;