----------------------------------------------------------------------------
--  scan_vga.vhd
--	Scan Generator for VGA
--	Version 1.0
--
--  Copyright (C) 2014 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
----------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;

use work.vivado_pkg.ALL;	-- Vivado Attributes


entity scan_vga is
    port (
	clk	: in std_logic;				-- Scan CLK
	reset	: in std_logic;				-- # Reset
	--
	total_w : in std_logic_vector(11 downto 0);	-- Total Width
	total_h : in std_logic_vector(11 downto 0);	-- Total Heigth
	--
	hdisp_s : in std_logic_vector(11 downto 0);
	hdisp_e : in std_logic_vector(11 downto 0);
	vdisp_s : in std_logic_vector(11 downto 0);
	vdisp_e : in std_logic_vector(11 downto 0);
	--
	hsync_s : in std_logic_vector(11 downto 0);
	hsync_e : in std_logic_vector(11 downto 0);
	vsync_s : in std_logic_vector(11 downto 0);
	vsync_e : in std_logic_vector(11 downto 0);
	--
	blank	: out std_logic;
	hsync	: out std_logic;
	vsync	: out std_logic;
	--
	hpos	: out std_logic_vector(11 downto 0);
	vpos	: out std_logic_vector(11 downto 0);
	frame	: out std_logic
    );
end entity scan_vga;


architecture RTL of scan_vga is

    attribute KEEP_HIERARCHY of RTL : architecture is "TRUE";

    signal cnt_h : unsigned(11 downto 0) := x"000";
    signal cnt_v : unsigned(11 downto 0) := x"000";

    signal ab : std_logic_vector(47 downto 0);

    alias a : std_logic_vector(29 downto 0) is ab(47 downto 18);
    alias b : std_logic_vector(17 downto 0) is ab(17 downto 0);

    alias lim_h : std_logic_vector(11 downto 0) is ab(11 downto 0);
    alias lim_v : std_logic_vector(11 downto 0) is ab(23 downto 12);
    alias lim_x : std_logic_vector(23 downto 0) is ab(47 downto 24);

    signal c : std_logic_vector(47 downto 0);

    alias c_cnt_h : std_logic_vector(11 downto 0) is c(11 downto 0);
    alias c_cnt_v : std_logic_vector(11 downto 0) is c(23 downto 12);
    alias c_cnt_x : std_logic_vector(23 downto 0) is c(47 downto 24);

    signal carry : std_logic_vector(3 downto 0);

    signal disp : std_logic_vector(3 downto 0);
    signal sync : std_logic_vector(3 downto 0);

begin

    lim_h <= total_w;
    lim_v <= total_h;
    lim_x <= (others => '0');

    c_cnt_h <= std_logic_vector(cnt_h);
    c_cnt_v <= std_logic_vector(cnt_v);
    c_cnt_x <= (others => '0');

    DSP48E1_limit_inst : entity work.dsp48_wrap
	generic map (
	    USE_SIMD => "FOUR12" )	-- SIMD selection ("ONE48", "TWO24", "FOUR12")
	port map (
	    CLK => clk,			-- 1-bit input: Clock input
	    A => a,			-- 30-bit input: A data input
	    B => b,			-- 18-bit input: B data input
	    C => c,			-- 48-bit input: C data input
	    ALUMODE => "0001",		-- 4-bit input: ALU control input
	    OPMODE => "0111011",	-- 7-bit input: Operation mode input
	    --
	    CARRYOUT => carry );	-- 4-bit carry output

    scan_proc : process (clk)
    begin
	if rising_edge(clk) then
	    frame <= '0';

	    if reset = '1' then
		cnt_h <= x"000";
		cnt_v <= x"000";

	    elsif carry(0) = '1' then
		if carry(1) = '1' then
		    cnt_v <= x"000";
		    frame <= '1';
		else
		    cnt_v <= cnt_v + "1";
		end if;

		cnt_h <= x"000";
	    else
		cnt_h <= cnt_h + "1";
	    end if;
	end if;
    end process;

    scan_comp_inst0 : entity work.scan_comp
	port map (
	    clk => clk,
	    reset => reset,
	    --
	    a0 => hdisp_s,
	    a1 => hdisp_e,
	    a2 => vdisp_s,
	    a3 => vdisp_e,
	    --
	    b0 => std_logic_vector(cnt_h),
	    b1 => std_logic_vector(cnt_h),
	    b2 => std_logic_vector(cnt_v),
	    b3 => std_logic_vector(cnt_v),
	    --
	    flags => disp );

    blank_proc : process (clk)
    begin
	if rising_edge(clk) then
	    if ((disp(0) xor disp(1)) and
		(disp(2) xor disp(3))) = '1' then
		hpos <= std_logic_vector(cnt_h);
		vpos <= std_logic_vector(cnt_v);
		blank <= '0';

	    else
		hpos <= (others => '1');
		vpos <= (others => '1');
		blank <= '1';

	    end if;
	end if;
    end process;

    scan_comp_inst1 : entity work.scan_comp
	port map (
	    clk => clk,
	    reset => reset,
	    --
	    a0 => hsync_s,
	    a1 => hsync_e,
	    a2 => vsync_s,
	    a3 => vsync_e,
	    --
	    b0 => std_logic_vector(cnt_h),
	    b1 => std_logic_vector(cnt_h),
	    b2 => std_logic_vector(cnt_v),
	    b3 => std_logic_vector(cnt_v),
	    --
	    flags => sync );

    sync_proc : process (clk)
    begin
	if rising_edge(clk) then
	    hsync <= sync(0) xor sync(1);
	    vsync <= sync(2) xor sync(3);
	end if;
    end process;

end RTL;