Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------
| Tool Version : Vivado v.2013.2 (lin64) Build 272601 Sat Jun 15 11:11:11 MDT 2013
| Date         : Sun Oct 27 05:32:34 2013
| Host         : neuromancer.lan running 64-bit Mageia 2
| Command      : report_utilization -hierarchical -file utilization.rpt
| Design       : top
| Device       : xc7z020
| Design State : Routed
-----------------------------------------------------------------------------------

Utilization Design Information

Table of Contents
-----------------
1. Utilization by Hierarchy

1. Utilization by Hierarchy
---------------------------

+--------------------------------------------+-------------------------------------------------+------------+------------+---------+------+------+--------+--------+--------------+
|                  Instance                  |                      Module                     | Total LUTs | Logic LUTs | LUTRAMs | SRLs |  FFs | RAMB36 | RAMB18 | DSP48 Blocks |
+--------------------------------------------+-------------------------------------------------+------------+------------+---------+------+------+--------+--------+--------------+
| top                                        |                                           (top) |       2830 |       2830 |       0 |    0 | 3692 |      4 |      0 |            0 |
|   (top)                                    |                                           (top) |          1 |          1 |       0 |    0 |  137 |      0 |      0 |            0 |
|   GEN_4TO1_256[0].comb256_4to1_inst        |                       data_4to1__parameterized0 |         72 |         72 |       0 |    0 |  262 |      0 |      0 |            0 |
|   GEN_4TO1_256[1].comb256_4to1_inst        |                    data_4to1__parameterized0_11 |         72 |         72 |       0 |    0 |  262 |      0 |      0 |            0 |
|   GEN_4TO1_64[0].comb64_4to1_inst          |                                     data_4to1_3 |          7 |          7 |       0 |    0 |   70 |      0 |      0 |            0 |
|   GEN_4TO1_64[1].comb64_4to1_inst          |                                    data_4to1_10 |          7 |          7 |       0 |    0 |   70 |      0 |      0 |            0 |
|   GEN_4TO1_64[2].comb64_4to1_inst          |                                     data_4to1_0 |          7 |          7 |       0 |    0 |   70 |      0 |      0 |            0 |
|   GEN_4TO1_64[3].comb64_4to1_inst          |                                     data_4to1_8 |          8 |          8 |       0 |    0 |   70 |      0 |      0 |            0 |
|   GEN_4TO1_64[4].comb64_4to1_inst          |                                     data_4to1_6 |          7 |          7 |       0 |    0 |   70 |      0 |      0 |            0 |
|   GEN_4TO1_64[5].comb64_4to1_inst          |                                       data_4to1 |          7 |          7 |       0 |    0 |   70 |      0 |      0 |            0 |
|   GEN_4TO1_64[6].comb64_4to1_inst          |                                     data_4to1_1 |          7 |          7 |       0 |    0 |   70 |      0 |      0 |            0 |
|   GEN_4TO1_64[7].comb64_4to1_inst          |                                     data_4to1_9 |          8 |          8 |       0 |    0 |   70 |      0 |      0 |            0 |
|   GEN_ADDR[0].FIFO_addr_inst               |   unimacro_FIFO_DUALCLOCK_MACRO__parameterized0 |          0 |          0 |       0 |    0 |    0 |      1 |      0 |            0 |
|   GEN_ADDR[1].FIFO_addr_inst               | unimacro_FIFO_DUALCLOCK_MACRO__parameterized0_5 |          2 |          2 |       0 |    0 |    0 |      1 |      0 |            0 |
|   GEN_FIFO[0].FIFO_data_inst               |                 unimacro_FIFO_DUALCLOCK_MACRO_4 |          0 |          0 |       0 |    0 |    0 |      1 |      0 |            0 |
|   GEN_FIFO[1].FIFO_data_inst               |                   unimacro_FIFO_DUALCLOCK_MACRO |          2 |          2 |       0 |    0 |    0 |      1 |      0 |            0 |
|   GEN_LVDS[0].cmv_deser_inst               |                                       cmv_deser |         35 |         35 |       0 |    0 |   56 |      0 |      0 |            0 |
|   GEN_LVDS[10].cmv_deser_inst              |                                   cmv_deser__23 |         35 |         35 |       0 |    0 |   56 |      0 |      0 |            0 |
|   GEN_LVDS[11].cmv_deser_inst              |                                   cmv_deser__22 |         35 |         35 |       0 |    0 |   56 |      0 |      0 |            0 |
|   GEN_LVDS[12].cmv_deser_inst              |                                   cmv_deser__21 |         34 |         34 |       0 |    0 |   56 |      0 |      0 |            0 |
|   GEN_LVDS[13].cmv_deser_inst              |                                   cmv_deser__20 |         35 |         35 |       0 |    0 |   56 |      0 |      0 |            0 |
|   GEN_LVDS[14].cmv_deser_inst              |                                   cmv_deser__19 |         35 |         35 |       0 |    0 |   56 |      0 |      0 |            0 |
|   GEN_LVDS[15].cmv_deser_inst              |                                   cmv_deser__18 |         35 |         35 |       0 |    0 |   56 |      0 |      0 |            0 |
|   GEN_LVDS[16].cmv_deser_inst              |                                   cmv_deser__17 |         34 |         34 |       0 |    0 |   56 |      0 |      0 |            0 |
|   GEN_LVDS[17].cmv_deser_inst              |                                   cmv_deser__16 |         35 |         35 |       0 |    0 |   56 |      0 |      0 |            0 |
|   GEN_LVDS[18].cmv_deser_inst              |                                   cmv_deser__15 |         35 |         35 |       0 |    0 |   56 |      0 |      0 |            0 |
|   GEN_LVDS[19].cmv_deser_inst              |                                   cmv_deser__14 |         35 |         35 |       0 |    0 |   56 |      0 |      0 |            0 |
|   GEN_LVDS[1].cmv_deser_inst               |                                   cmv_deser__32 |         35 |         35 |       0 |    0 |   56 |      0 |      0 |            0 |
|   GEN_LVDS[20].cmv_deser_inst              |                                   cmv_deser__13 |         35 |         35 |       0 |    0 |   56 |      0 |      0 |            0 |
|   GEN_LVDS[21].cmv_deser_inst              |                                   cmv_deser__12 |         35 |         35 |       0 |    0 |   56 |      0 |      0 |            0 |
|   GEN_LVDS[22].cmv_deser_inst              |                                   cmv_deser__11 |         35 |         35 |       0 |    0 |   56 |      0 |      0 |            0 |
|   GEN_LVDS[23].cmv_deser_inst              |                                   cmv_deser__10 |         35 |         35 |       0 |    0 |   56 |      0 |      0 |            0 |
|   GEN_LVDS[24].cmv_deser_inst              |                                    cmv_deser__9 |         40 |         40 |       0 |    0 |   56 |      0 |      0 |            0 |
|   GEN_LVDS[25].cmv_deser_inst              |                                    cmv_deser__8 |         35 |         35 |       0 |    0 |   56 |      0 |      0 |            0 |
|   GEN_LVDS[26].cmv_deser_inst              |                                    cmv_deser__7 |         35 |         35 |       0 |    0 |   56 |      0 |      0 |            0 |
|   GEN_LVDS[27].cmv_deser_inst              |                                    cmv_deser__6 |         35 |         35 |       0 |    0 |   56 |      0 |      0 |            0 |
|   GEN_LVDS[28].cmv_deser_inst              |                                    cmv_deser__5 |         35 |         35 |       0 |    0 |   56 |      0 |      0 |            0 |
|   GEN_LVDS[29].cmv_deser_inst              |                                    cmv_deser__4 |         34 |         34 |       0 |    0 |   56 |      0 |      0 |            0 |
|   GEN_LVDS[2].cmv_deser_inst               |                                   cmv_deser__31 |         35 |         35 |       0 |    0 |   56 |      0 |      0 |            0 |
|   GEN_LVDS[30].cmv_deser_inst              |                                    cmv_deser__3 |         35 |         35 |       0 |    0 |   56 |      0 |      0 |            0 |
|   GEN_LVDS[31].cmv_deser_inst              |                                    cmv_deser__2 |         35 |         35 |       0 |    0 |   56 |      0 |      0 |            0 |
|   GEN_LVDS[32].cmv_deser_inst              |                                    cmv_deser__1 |         35 |         35 |       0 |    0 |   54 |      0 |      0 |            0 |
|   GEN_LVDS[3].cmv_deser_inst               |                                   cmv_deser__30 |         35 |         35 |       0 |    0 |   56 |      0 |      0 |            0 |
|   GEN_LVDS[4].cmv_deser_inst               |                                   cmv_deser__29 |         36 |         36 |       0 |    0 |   56 |      0 |      0 |            0 |
|   GEN_LVDS[5].cmv_deser_inst               |                                   cmv_deser__28 |         35 |         35 |       0 |    0 |   56 |      0 |      0 |            0 |
|   GEN_LVDS[6].cmv_deser_inst               |                                   cmv_deser__27 |         35 |         35 |       0 |    0 |   56 |      0 |      0 |            0 |
|   GEN_LVDS[7].cmv_deser_inst               |                                   cmv_deser__26 |         40 |         40 |       0 |    0 |   56 |      0 |      0 |            0 |
|   GEN_LVDS[8].cmv_deser_inst               |                                   cmv_deser__25 |         35 |         35 |       0 |    0 |   56 |      0 |      0 |            0 |
|   GEN_LVDS[9].cmv_deser_inst               |                                   cmv_deser__24 |         39 |         39 |       0 |    0 |   56 |      0 |      0 |            0 |
|   GEN_WRITER[0].WRITER0.addr_gen_inst      |                                        addr_gen |          9 |          9 |       0 |    0 |   25 |      0 |      0 |            0 |
|   GEN_WRITER[0].WRITER0.axihp_writer_inst0 |                    axihp_writer__parameterized0 |         17 |         17 |       0 |    0 |   13 |      0 |      0 |            0 |
|   GEN_WRITER[1].WRITER1.addr_gen_inst      |                                      addr_gen_2 |          9 |          9 |       0 |    0 |   25 |      0 |      0 |            0 |
|   GEN_WRITER[1].WRITER1.axihp_writer_inst2 |                                    axihp_writer |         17 |         17 |       0 |    0 |   13 |      0 |      0 |            0 |
|   axi_lite_inst0                           |                                        axi_lite |          6 |          6 |       0 |    0 |   12 |      0 |      0 |            0 |
|   axi_split_inst0                          |                                       axi_split |         33 |         33 |       0 |    0 |    8 |      0 |      0 |            0 |
|   axi_split_inst1                          |                       axi_split__parameterized0 |         28 |         28 |       0 |    0 |    8 |      0 |      0 |            0 |
|   div_lvds_inst0                           |                                       async_div |         28 |         28 |       0 |    0 |   28 |      0 |      0 |            0 |
|   div_lvds_inst1                           |                                     async_div_7 |         28 |         28 |       0 |    0 |   28 |      0 |      0 |            0 |
|   lvds_pll_inst                            |                                        lvds_pll |          1 |          1 |       0 |    0 |    0 |      0 |      0 |            0 |
|   pmod_dbg_jc_inst                         |                                      pmod_debug |         43 |         43 |       0 |    0 |   24 |      0 |      0 |            0 |
|     (pmod_dbg_jc_inst)                     |                                      pmod_debug |         31 |         31 |       0 |    0 |   12 |      0 |      0 |            0 |
|     async_div_inst                         |                       async_div__parameterized0 |         12 |         12 |       0 |    0 |   12 |      0 |      0 |            0 |
|   pmod_dbg_jd_inst                         |                                   pmod_debug__1 |         43 |         43 |       0 |    0 |   24 |      0 |      0 |            0 |
|     (pmod_dbg_jd_inst)                     |                                   pmod_debug__1 |         31 |         31 |       0 |    0 |   12 |      0 |      0 |            0 |
|     async_div_inst                         |                    async_div__parameterized0_12 |         12 |         12 |       0 |    0 |   12 |      0 |      0 |            0 |
|   ps7_stub_inst                            |                                        ps7_stub |         51 |         51 |       0 |    0 |    0 |      0 |      0 |            0 |
|   reg_delay_inst                           |                                       reg_delay |        269 |        269 |       0 |    0 |  149 |      0 |      0 |            0 |
|   reg_file_inst                            |                                        reg_file |        815 |        815 |       0 |    0 |  205 |      0 |      0 |            0 |
|   reg_spi_inst                             |                                         reg_spi |         61 |         61 |       0 |    0 |   63 |      0 |      0 |            0 |
|     (reg_spi_inst)                         |                                         reg_spi |         14 |         14 |       0 |    0 |   33 |      0 |      0 |            0 |
|     spi_inst                               |                                         cmv_spi |         47 |         47 |       0 |    0 |   30 |      0 |      0 |            0 |
+--------------------------------------------+-------------------------------------------------+------------+------------+---------+------+------+--------+--------+--------------+
* Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining


Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------
| Tool Version : Vivado v.2013.2 (lin64) Build 272601 Sat Jun 15 11:11:11 MDT 2013
| Date         : Sun Oct 27 05:32:35 2013
| Host         : neuromancer.lan running 64-bit Mageia 2
| Command      : report_clock_utilization -file utilization.rpt -append
| Design       : top
| Device       : xc7z020
-----------------------------------------------------------------------------------

Clock Utilization Report

Table of Contents
-----------------
1. Clock Primitive Utilization
2. Details of Global Clocks
3. Details of Regional Clocks
4. Details of Multi-Regional Clocks
5. Details of Local Clocks
6. Clock Regions : Key Resource Utilization
7. Net wise resources used in clock region X0Y0
8. Net wise resources used in clock region X1Y0
9. Net wise resources used in clock region X0Y1
10. Net wise resources used in clock region X1Y1
11. Net wise resources used in clock region X0Y2
12. Net wise resources used in clock region X1Y2

1. Clock Primitive Utilization
------------------------------

+-------+------+-----------+------------+
| Type  | Used | Available | Num Locked |
+-------+------+-----------+------------+
| BUFG  |    8 |        32 |          0 |
| BUFH  |    0 |        72 |          0 |
| BUFIO |    0 |        16 |          0 |
| MMCM  |    1 |         4 |          0 |
| BUFR  |    0 |        16 |          0 |
| BUFMR |    0 |         8 |          0 |
+-------+------+-----------+------------+


2. Details of Global Clocks
---------------------------

+-------+-------------------------------------+---------------------------+--------------+--------+---------------+-----------+
|       |                                     |                           |   Num Loads  |        |               |           |
+-------+-------------------------------------+---------------------------+------+-------+--------+---------------+-----------+
| Index | BUFG Cell                           | Net Name                  | BELs | Sites | Locked | MaxDelay (ns) | Skew (ns) |
+-------+-------------------------------------+---------------------------+------+-------+--------+---------------+-----------+
|     1 | lvds_pll_inst/BUFG_inst             | lvds_pll_inst/O           |    1 |     1 |     no |         1.980 |     0.210 |
|     2 | lvds_pll_inst/GEN_BUF0[0].BUFG_inst | lvds_pll_inst/pll_clk[0]  |    2 |     2 |     no |         3.156 |     1.364 |
|     3 | lvds_pll_inst/GEN_BUF0[5].BUFG_inst | lvds_pll_inst/pll_clk[3]  |   31 |    10 |     no |         2.284 |     0.534 |
|     4 | lvds_pll_inst/GEN_BUF0[2].BUFG_inst | lvds_pll_inst/pll_clk[1]  |   33 |    22 |     no |         1.849 |     0.473 |
|     5 | lvds_pll_inst/GEN_BUF1[2].BUFG_inst | lvds_pll_inst/lvds_clk[1] |   52 |    10 |     no |         1.936 |     0.427 |
|     6 | lvds_pll_inst/GEN_BUF1[4].BUFG_inst | lvds_pll_inst/lvds_clk[2] |  104 |    60 |     no |         2.139 |     0.469 |
|     7 | lvds_pll_inst/GEN_BUF0[4].BUFG_inst | lvds_pll_inst/pll_clk[2]  |  346 |   124 |     no |         3.140 |     1.574 |
|     8 | lvds_pll_inst/GEN_BUF1[1].BUFG_inst | lvds_pll_inst/lvds_clk[0] | 3103 |  1178 |     no |         2.418 |     0.794 |
+-------+-------------------------------------+---------------------------+------+-------+--------+---------------+-----------+


+-------+------------------------------+-----------------------------------+--------------+--------+---------------+-----------+
|       |                              |                                   |   Num Loads  |        |               |           |
+-------+------------------------------+-----------------------------------+------+-------+--------+---------------+-----------+
| Index | MMCM Cell                    | Net Name                          | BELs | Sites | Locked | MaxDelay (ns) | Skew (ns) |
+-------+------------------------------+-----------------------------------+------+-------+--------+---------------+-----------+
|     1 | lvds_pll_inst/lvds_mmcm_inst | lvds_pll_inst/n_2_lvds_mmcm_inst  |    0 |     0 |     no |         0.000 |     0.000 |
|     2 | lvds_pll_inst/lvds_mmcm_inst | lvds_pll_inst/n_4_lvds_mmcm_inst  |    0 |     0 |     no |         0.000 |     0.000 |
|     3 | lvds_pll_inst/lvds_mmcm_inst | lvds_pll_inst/n_10_lvds_mmcm_inst |    0 |     0 |     no |         0.000 |     0.000 |
|     4 | lvds_pll_inst/lvds_mmcm_inst | lvds_pll_inst/n_0_lvds_mmcm_inst  |    1 |     1 |     no |         2.206 |     0.194 |
|     5 | lvds_pll_inst/lvds_mmcm_inst | lvds_pll_inst/n_6_lvds_mmcm_inst  |    1 |     1 |     no |         2.206 |     0.194 |
|     6 | lvds_pll_inst/lvds_mmcm_inst | lvds_pll_inst/n_8_lvds_mmcm_inst  |    1 |     1 |     no |         2.206 |     0.194 |
|     7 | lvds_pll_inst/lvds_mmcm_inst | lvds_pll_inst/n_11_lvds_mmcm_inst |    1 |     1 |     no |         2.206 |     0.194 |
+-------+------------------------------+-----------------------------------+------+-------+--------+---------------+-----------+


3. Details of Regional Clocks
-----------------------------

4. Details of Multi-Regional Clocks
-----------------------------------

5. Details of Local Clocks
--------------------------

6. Clock Regions : Key Resource Utilization
-------------------------------------------

+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
|                   | Global Clock |     BUFRs    |    BUFMRs    |    BUFIOs    |     MMCM     |      PLL     |      GT      |      PCI     |    ILOGIC    |    OLOGIC    |      FF      |     LUTM     |    RAMB18    |    RAMB36    |    DSP48E1   |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| X0Y0              |    2 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    1 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |  111 | 20000 |    0 |  4000 |    0 |   120 |    0 |    30 |    0 |    60 |
| X1Y0              |    2 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |   56 | 25600 |    0 |  3400 |    0 |   120 |    0 |    30 |    0 |    40 |
| X0Y1              |    3 |    12 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |   46 |  9600 |    0 |  1600 |    0 |    40 |    2 |    10 |    0 |    20 |
| X1Y1              |    6 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |   16 |    50 |    0 |    50 | 2323 | 20800 |    0 |  3400 |    0 |   120 |    2 |    30 |    0 |    40 |
| X0Y2              |    2 |    12 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |  9600 |    0 |  1600 |    0 |    36 |    0 |     9 |    0 |    20 |
| X1Y2              |    5 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    1 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |   17 |    50 |    0 |    50 | 1156 | 20800 |    0 |  3400 |    0 |   108 |    0 |    27 |    0 |    40 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
* RAMB36 site can be used as two RAMB18/FIFO18 sites


7. Net wise resources used in clock region X0Y0
-----------------------------------------------

+-------------+--------+-----------+-----------+---------+---------+-----+-------+----------+------+--------------------------+
| Source Type | Locked | MMCM Pins | BRAM Pins | ILOGICs | OLOGICs | FFs | LUTMs | DSP48E1s | PLLs |           Clock Net Name |
+-------------+--------+-----------+-----------+---------+---------+-----+-------+----------+------+--------------------------+
| BUFG        |   no   |         0 |         0 |       0 |       0 |  30 |     0 |        0 |    0 | lvds_pll_inst/pll_clk[3] |
| BUFG        |   no   |         0 |         0 |       0 |       0 |  33 |     0 |        0 |    0 | lvds_pll_inst/pll_clk[2] |
+-------------+--------+-----------+-----------+---------+---------+-----+-------+----------+------+--------------------------+


8. Net wise resources used in clock region X1Y0
-----------------------------------------------

+-------------+--------+-----------+-----------+---------+---------+-----+-------+----------+------+---------------------------+
| Source Type | Locked | MMCM Pins | BRAM Pins | ILOGICs | OLOGICs | FFs | LUTMs | DSP48E1s | PLLs |            Clock Net Name |
+-------------+--------+-----------+-----------+---------+---------+-----+-------+----------+------+---------------------------+
| BUFG        |   no   |         0 |         0 |       0 |       0 |   1 |     0 |        0 |    0 | lvds_pll_inst/lvds_clk[0] |
| BUFG        |   no   |         0 |         0 |       0 |       0 |   1 |     0 |        0 |    0 | lvds_pll_inst/pll_clk[0]  |
+-------------+--------+-----------+-----------+---------+---------+-----+-------+----------+------+---------------------------+


9. Net wise resources used in clock region X0Y1
-----------------------------------------------

+-------------+--------+-----------+-----------+---------+---------+-----+-------+----------+------+---------------------------+
| Source Type | Locked | MMCM Pins | BRAM Pins | ILOGICs | OLOGICs | FFs | LUTMs | DSP48E1s | PLLs |            Clock Net Name |
+-------------+--------+-----------+-----------+---------+---------+-----+-------+----------+------+---------------------------+
| BUFG        |   no   |         0 |         2 |       0 |       0 |   0 |     0 |        0 |    0 | lvds_pll_inst/lvds_clk[1] |
| BUFG        |   no   |         0 |         0 |       0 |       0 |  20 |     0 |        0 |    0 | lvds_pll_inst/pll_clk[2]  |
| BUFG        |   no   |         0 |         2 |       0 |       0 |  26 |     0 |        0 |    0 | lvds_pll_inst/pll_clk[1]  |
+-------------+--------+-----------+-----------+---------+---------+-----+-------+----------+------+---------------------------+


10. Net wise resources used in clock region X1Y1
------------------------------------------------

+-------------+--------+-----------+-----------+---------+---------+------+-------+----------+------+---------------------------+
| Source Type | Locked | MMCM Pins | BRAM Pins | ILOGICs | OLOGICs |  FFs | LUTMs | DSP48E1s | PLLs |            Clock Net Name |
+-------------+--------+-----------+-----------+---------+---------+------+-------+----------+------+---------------------------+
| BUFG        |   no   |         0 |         0 |       0 |       0 |   50 |     0 |        0 |    0 | lvds_pll_inst/lvds_clk[1] |
| BUFG        |   no   |         0 |         2 |      16 |       0 | 1969 |     0 |        0 |    0 | lvds_pll_inst/lvds_clk[0] |
| BUFG        |   no   |         0 |         0 |       0 |       0 |  272 |     0 |        0 |    0 | lvds_pll_inst/pll_clk[2]  |
| BUFG        |   no   |         0 |         0 |       0 |       0 |   32 |     0 |        0 |    0 | lvds_pll_inst/lvds_clk[2] |
| BUFG        |   no   |         0 |         2 |       0 |       0 |    0 |     0 |        0 |    0 | lvds_pll_inst/pll_clk[1]  |
+-------------+--------+-----------+-----------+---------+---------+------+-------+----------+------+---------------------------+


11. Net wise resources used in clock region X0Y2
------------------------------------------------

+-------------+--------+-----------+-----------+---------+---------+-----+-------+----------+------+--------------------------+
| Source Type | Locked | MMCM Pins | BRAM Pins | ILOGICs | OLOGICs | FFs | LUTMs | DSP48E1s | PLLs |           Clock Net Name |
+-------------+--------+-----------+-----------+---------+---------+-----+-------+----------+------+--------------------------+
| BUFG        |   no   |         0 |         0 |       0 |       0 |   0 |     0 |        0 |    0 | lvds_pll_inst/pll_clk[2] |
| BUFG        |   no   |         0 |         0 |       0 |       0 |   0 |     0 |        0 |    0 | lvds_pll_inst/pll_clk[1] |
+-------------+--------+-----------+-----------+---------+---------+-----+-------+----------+------+--------------------------+


12. Net wise resources used in clock region X1Y2
------------------------------------------------

+-------------+--------+-----------+-----------+---------+---------+------+-------+----------+------+---------------------------+
| Source Type | Locked | MMCM Pins | BRAM Pins | ILOGICs | OLOGICs |  FFs | LUTMs | DSP48E1s | PLLs |            Clock Net Name |
+-------------+--------+-----------+-----------+---------+---------+------+-------+----------+------+---------------------------+
| BUFG        |   no   |         0 |         0 |      17 |       0 | 1098 |     0 |        0 |    0 | lvds_pll_inst/lvds_clk[0] |
| BUFG        |   no   |         0 |         0 |       0 |       0 |   19 |     0 |        0 |    0 | lvds_pll_inst/pll_clk[2]  |
| BUFG        |   no   |         1 |         0 |       0 |       0 |    0 |     0 |        0 |    0 | lvds_pll_inst/O           |
| BUFG        |   no   |         0 |         0 |       0 |       0 |   39 |     0 |        0 |    0 | lvds_pll_inst/lvds_clk[2] |
+-------------+--------+-----------+-----------+---------+---------+------+-------+----------+------+---------------------------+



# Location of BUFG Primitives 
set_property LOC BUFGCTRL_X0Y19 [get_cells lvds_pll_inst/BUFG_inst]
set_property LOC BUFGCTRL_X0Y3 [get_cells lvds_pll_inst/GEN_BUF0[0].BUFG_inst]
set_property LOC BUFGCTRL_X0Y2 [get_cells lvds_pll_inst/GEN_BUF0[5].BUFG_inst]
set_property LOC BUFGCTRL_X0Y1 [get_cells lvds_pll_inst/GEN_BUF0[2].BUFG_inst]
set_property LOC BUFGCTRL_X0Y18 [get_cells lvds_pll_inst/GEN_BUF1[2].BUFG_inst]
set_property LOC BUFGCTRL_X0Y17 [get_cells lvds_pll_inst/GEN_BUF1[4].BUFG_inst]
set_property LOC BUFGCTRL_X0Y0 [get_cells lvds_pll_inst/GEN_BUF0[4].BUFG_inst]
set_property LOC BUFGCTRL_X0Y16 [get_cells lvds_pll_inst/GEN_BUF1[1].BUFG_inst]

# Location of IO Clock Primitives

# Location of MMCM Clock Primitives
set_property LOC MMCME2_ADV_X1Y2 [get_cells lvds_pll_inst/lvds_mmcm_inst]

# Location of BUFH Clock Primitives

# Location of BUFR Clock Primitives

# Location of BUFMR Clock Primitives

# Location of PLL Clock Primitives
set_property LOC PLLE2_ADV_X0Y0 [get_cells lvds_pll_inst/lvds_pll_inst]

# Location of IO Primitives which is load of clock spine
set_property LOC IOB_X1Y76 [get_cells OBUFDS_inst]
set_property LOC IOB_X0Y45 [get_cells cmv_clk_OBUF_inst]
set_property LOC IOB_X1Y46 [get_cells led_OBUF[0]_inst]

# Location of clock ports
set_property LOC IOB_X1Y125 [get_ports cmv_lvds_outclk_n]
set_property LOC IOB_X1Y126 [get_ports cmv_lvds_outclk_p]

# Clock net "lvds_pll_inst/pll_clk[0]" driven by instance "lvds_pll_inst/GEN_BUF0[0].BUFG_inst" located at site "BUFGCTRL_X0Y3"
#startgroup
create_pblock CLKAG_lvds_pll_inst/pll_clk[0]
add_cells_to_pblock [get_pblocks  CLKAG_lvds_pll_inst/pll_clk[0]] [get_cells  -filter { IS_PRIMITIVE==1 && NAME!=OBUFDS_inst} -of_object [get_pins -leaf -filter {DIRECTION==IN} -of_objects [get_nets lvds_pll_inst/pll_clk[0]]]]
resize_pblock [get_pblocks CLKAG_lvds_pll_inst/pll_clk[0]] -add {CLOCKREGION_X1Y0:CLOCKREGION_X1Y0}
#endgroup

# Clock net "lvds_pll_inst/pll_clk[1]" driven by instance "lvds_pll_inst/GEN_BUF0[2].BUFG_inst" located at site "BUFGCTRL_X0Y1"
#startgroup
create_pblock CLKAG_lvds_pll_inst/pll_clk[1]
add_cells_to_pblock [get_pblocks  CLKAG_lvds_pll_inst/pll_clk[1]] [get_cells  -filter { IS_PRIMITIVE==1 } -of_object [get_pins -leaf -filter {DIRECTION==IN} -of_objects [get_nets lvds_pll_inst/pll_clk[1]]]]
resize_pblock [get_pblocks CLKAG_lvds_pll_inst/pll_clk[1]] -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
#endgroup

# Clock net "lvds_pll_inst/pll_clk[2]" driven by instance "lvds_pll_inst/GEN_BUF0[4].BUFG_inst" located at site "BUFGCTRL_X0Y0"
#startgroup
create_pblock CLKAG_lvds_pll_inst/pll_clk[2]
add_cells_to_pblock [get_pblocks  CLKAG_lvds_pll_inst/pll_clk[2]] [get_cells  -filter { IS_PRIMITIVE==1 && NAME!=cmv_clk_OBUF_inst} -of_object [get_pins -leaf -filter {DIRECTION==IN} -of_objects [get_nets lvds_pll_inst/pll_clk[2]]]]
resize_pblock [get_pblocks CLKAG_lvds_pll_inst/pll_clk[2]] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
#endgroup

# Clock net "lvds_pll_inst/pll_clk[3]" driven by instance "lvds_pll_inst/GEN_BUF0[5].BUFG_inst" located at site "BUFGCTRL_X0Y2"
#startgroup
create_pblock CLKAG_lvds_pll_inst/pll_clk[3]
add_cells_to_pblock [get_pblocks  CLKAG_lvds_pll_inst/pll_clk[3]] [get_cells  -filter { IS_PRIMITIVE==1 } -of_object [get_pins -leaf -filter {DIRECTION==IN} -of_objects [get_nets lvds_pll_inst/pll_clk[3]]]]
resize_pblock [get_pblocks CLKAG_lvds_pll_inst/pll_clk[3]] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0}
#endgroup

# Clock net "lvds_pll_inst/lvds_clk[0]" driven by instance "lvds_pll_inst/GEN_BUF1[1].BUFG_inst" located at site "BUFGCTRL_X0Y16"
#startgroup
create_pblock CLKAG_lvds_pll_inst/lvds_clk[0]
add_cells_to_pblock [get_pblocks  CLKAG_lvds_pll_inst/lvds_clk[0]] [get_cells  -filter { IS_PRIMITIVE==1 } -of_object [get_pins -leaf -filter {DIRECTION==IN} -of_objects [get_nets lvds_pll_inst/lvds_clk[0]]]]
resize_pblock [get_pblocks CLKAG_lvds_pll_inst/lvds_clk[0]] -add {CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
#endgroup

# Clock net "lvds_pll_inst/lvds_clk[1]" driven by instance "lvds_pll_inst/GEN_BUF1[2].BUFG_inst" located at site "BUFGCTRL_X0Y18"
#startgroup
create_pblock CLKAG_lvds_pll_inst/lvds_clk[1]
add_cells_to_pblock [get_pblocks  CLKAG_lvds_pll_inst/lvds_clk[1]] [get_cells  -filter { IS_PRIMITIVE==1 } -of_object [get_pins -leaf -filter {DIRECTION==IN} -of_objects [get_nets lvds_pll_inst/lvds_clk[1]]]]
resize_pblock [get_pblocks CLKAG_lvds_pll_inst/lvds_clk[1]] -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1}
#endgroup

# Clock net "lvds_pll_inst/lvds_clk[2]" driven by instance "lvds_pll_inst/GEN_BUF1[4].BUFG_inst" located at site "BUFGCTRL_X0Y17"
#startgroup
create_pblock CLKAG_lvds_pll_inst/lvds_clk[2]
add_cells_to_pblock [get_pblocks  CLKAG_lvds_pll_inst/lvds_clk[2]] [get_cells  -filter { IS_PRIMITIVE==1 } -of_object [get_pins -leaf -filter {DIRECTION==IN} -of_objects [get_nets lvds_pll_inst/lvds_clk[2]]]]
resize_pblock [get_pblocks CLKAG_lvds_pll_inst/lvds_clk[2]] -add {CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
#endgroup

# Clock net "lvds_pll_inst/CLKFBIN" driven by instance "lvds_pll_inst/lvds_pll_inst" located at site "PLLE2_ADV_X0Y0"
#startgroup
create_pblock CLKAG_lvds_pll_inst/CLKFBIN
add_cells_to_pblock [get_pblocks  CLKAG_lvds_pll_inst/CLKFBIN] [get_cells  -filter { IS_PRIMITIVE==1 } -of_object [get_pins -leaf -filter {DIRECTION==IN} -of_objects [get_nets lvds_pll_inst/CLKFBIN]]]
resize_pblock [get_pblocks CLKAG_lvds_pll_inst/CLKFBIN] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0}
#endgroup
