----------------------------------------------------------------------------
--  fifo_reset.vhd
--	FIFO Reset Manager
--	Version 1.0
--
--  Copyright (C) 2013 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
----------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.ALL;

entity fifo_reset is
    port (
	wclk	: in std_logic;
	rclk	: in std_logic;
	reset	: in std_logic;
	--
	fifo_wrst : out std_logic;
	fifo_wrdy : out std_logic;
	fifo_rrst : out std_logic;
	fifo_rrdy : out std_logic );

end entity fifo_reset;


architecture RTL of fifo_reset is

begin

    wreset_proc : process(wclk, reset)

	variable wcnt_v : natural range 7 downto 0;

	variable wrdy_v : std_logic := '0';
	variable wrst_v : std_logic := '0';

	type state_t is (ready_s, delay_s, reset_s, post_s);

	variable wstate : state_t := delay_s;

    begin

	if rising_edge(wclk) then
	    case wstate is
		when ready_s =>			-- fifo write ready
		    wrdy_v := '1';
		    if reset = '1' then
			wstate := delay_s;
		    end if;

		when delay_s =>			-- delay by 1 wclk
		    wrdy_v := '0';
		    wcnt_v := 4;
		    wstate := reset_s;

		when reset_s =>			-- 5 wclk reset
		    wrst_v := '1';
		    if wcnt_v = 0 then
			wstate := post_s;
		    else
			wcnt_v := wcnt_v - 1;
		    end if;

		when post_s =>			-- delay by 3 wclk
		    wrst_v := '0';
		    if wcnt_v = 2 then
			wstate := ready_s;
		    else
			wcnt_v := wcnt_v + 1;
		    end if;

	    end case;
	end if;

	fifo_wrdy <= wrdy_v;
	fifo_wrst <= wrst_v;

    end process;


    rreset_proc : process(rclk, reset)

	variable rcnt_v : natural range 7 downto 0;

	variable rrdy_v : std_logic := '0';
	variable rrst_v : std_logic := '0';

	type state_t is (ready_s, delay_s, reset_s, post_s);

	variable rstate : state_t := delay_s;

    begin

	if rising_edge(rclk) then
	    case rstate is
		when ready_s =>			-- fifo read ready
		    rrdy_v := '1';
		    if reset = '1' then
			rstate := delay_s;
		    end if;

		when delay_s =>			-- delay by 1 rclk
		    rrdy_v := '0';
		    rcnt_v := 4;
		    rstate := reset_s;

		when reset_s =>			-- 5 rclk reset
		    rrst_v := '1';
		    if rcnt_v = 0 then
			rstate := post_s;
		    else
			rcnt_v := rcnt_v - 1;
		    end if;

		when post_s =>			-- delay by 3 rclk
		    rrst_v := '0';
		    if rcnt_v = 2 then
			rstate := ready_s;
		    else
			rcnt_v := rcnt_v + 1;
		    end if;

	    end case;
	end if;

	fifo_rrdy <= rrdy_v;
	fifo_rrst <= rrst_v;

    end process;

end RTL;