----------------------------------------------------------------------------
--  blink_plps.vhd
--	ZedBoard simple VHDL example
--	Version 1.0
--
--  Copyright (C) 2013 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
--
--  xflow -p xc7z020clg484-1 -synth xst_vhdl.opt blink_plps.prj
--  xflow -p xc7z020clg484-1 -implement balanced.opt -config bitgen.opt blink_plps.ngc
--  promgen -w -b -p bin -o blink_plps.bin -u 0 blink_plps.bit -data_width 32
--
--	0xe000a010 rw	ps7::gpio::MASK_DATA_2_LSW
--	0xe000a014 rw	ps7::gpio::MASK_DATA_2_MSW
--	0xe000a048 rw	ps7::gpio::DATA_2
--	0xe000a068 ro	ps7::gpio::DATA_2_RO
--	0xe000a284 rw	ps7::gpio::DIRM_2
--	0xe000a288 rw	ps7::gpio::OEN_2
--
--	0xf8000170 rw	ps7::slcr::FPGA0_CLK_CTRL
--	0xf8000174 rw	ps7::slcr::FPGA0_THR_CTRL
--	0xf8000178 rw	ps7::slcr::FPGA0_THR_CNT
--	0xf800017c ro	ps7::slcr::FPGA0_THR_STA
--
--	same for 0xf80001[89a]0 and FPGA[123]
--
--	0xf8000240 rw	ps7::slcr::FPGA_RST_CTRL
--
----------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;

entity divider is
    generic (
	RATIO : integer := 10000000
    );
    port (
	clk_in	: in std_logic;		-- input clock
	enable	: in std_logic;		-- enable divider
	--
	clk_out : out std_logic		-- output clk_in
    );
end entity divider;

architecture RTL of divider is
begin
    divide_proc : process(clk_in, enable)
    variable count : integer range 0 to RATIO - 1;
    begin
	if enable = '0' then		-- reset
	    count := 0;
	elsif rising_edge(clk_in) then	-- clk
	    if count = RATIO - 1 then
		count := 0;
	    else
		count := count + 1;
	    end if;
	end if;
	
	if count < RATIO / 2 then
	    clk_out <= '0';
	else
	    clk_out <= '1';
	end if;
    end process;
end RTL;




library IEEE;
use IEEE.std_logic_1164.all;

entity top is
    port (
	swi	: in std_logic_vector(7 downto 0);	-- Switch: '1' is up
	--
	led	: out std_logic_vector(7 downto 0)	-- LED: '1' to turn on
    );

    attribute LOC      : string;	-- Pin Location
    attribute IOSTANDARD : string;	-- LVTTL33, LVCMOS33 etc.
    attribute PERIOD : string;		-- clock period

    attribute LOC of swi: signal is "M15 H17 H18 H19 F21 H22 G22 F22";
    attribute IOSTANDARD of swi: signal is "LVCMOS33";

    attribute LOC of led: signal is "U14 U19 W22 V22 U21 U22 T21 T22";
    attribute IOSTANDARD of led: signal is "LVCMOS33";

end entity top;


architecture RTL of top is
    component ps7_stub
	port (
	    ps_fclk : out std_logic_vector(3 downto 0);
	    ps_resetn : out std_logic_vector(3 downto 0);
	    --
	    gpio_i : in std_logic_vector(63 downto 0);
	    gpio_o : out std_logic_vector(63 downto 0);
	    gpio_tn : out std_logic_vector(63 downto 0)
	);
    end component ps7_stub;

    component DIVIDER
	generic (
	    RATIO : integer
	);
	port (
	    clk_in  : in std_logic;
	    enable  : in std_logic;
	    --
	    clk_out : out std_logic
	);
    end component divider;

    signal fclk : std_logic_vector(3 downto 0);
    signal resetn : std_logic_vector(3 downto 0);

    signal gpio_i : std_logic_vector(63 downto 0);
    signal gpio_o : std_logic_vector(63 downto 0);
    signal gpio_tn : std_logic_vector(63 downto 0);

    attribute buffer_type : string;	-- [io]buf[ghr][p]|none
    attribute buffer_type of fclk: signal is "bufg";
    attribute buffer_type of gpio_o: signal is "bufg";
    attribute buffer_type of gpio_tn: signal is "bufg";

begin
    ps7_stub_inst : ps7_stub
    port map ( ps_fclk => fclk, ps_resetn => resetn,
	gpio_i => gpio_i, gpio_o => gpio_o, gpio_tn => gpio_tn );

    GEN_DIVIDER: for I in 0 to 3 generate
	DIVIDER_inst : DIVIDER
	    generic map ( RATIO => 10_000_000 )
	    port map ( clk_in => fclk(I), enable => resetn(I), clk_out => led(I));
    end generate GEN_DIVIDER;

    led(7 downto 6) <= gpio_o(1 downto 0);
    led(5 downto 4) <= gpio_tn(1 downto 0);
    gpio_i(15 downto 8) <= swi;
end RTL;