---------------------------------------------------------------------------- -- blink_pll.vhd -- ZedBoard simple VHDL example -- Version 1.0 -- -- Copyright (C) 2013 H.Poetzl -- -- This program is free software: you can redistribute it and/or -- modify it under the terms of the GNU General Public License -- as published by the Free Software Foundation, either version -- 2 of the License, or (at your option) any later version. -- -- xflow -p xc7z020clg484-1 -synth xst_vhdl.opt blink_pll.vhd -- xflow -p xc7z020clg484-1 -implement balanced.opt -config bitgen.opt blink_pll.ngc -- promgen -w -b -p bin -o blink_pll.bin -u 0 blink_pll.bit -data_width 32 ---------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity divider is generic ( RATIO : integer := 10000000 ); port ( clk_in : in std_logic; -- input clock -- enable : in std_logic; -- enable divider -- clk_out : out std_logic -- output clk_in ); end entity divider; architecture RTL of divider is begin divide_proc : process(clk_in, enable) variable count : integer range 0 to RATIO - 1; begin if enable = '0' then -- reset count := 0; elsif rising_edge(clk_in) then -- clk if count = RATIO - 1 then count := 0; else count := count + 1; end if; end if; if count < RATIO / 2 then clk_out <= '0'; else clk_out <= '1'; end if; end process; end RTL; library IEEE; use IEEE.std_logic_1164.all; Library UNISIM; use UNISIM.vcomponents.all; entity top is port ( clk : in std_logic; -- input clock to FPGA -- swi_0 : in std_logic; -- switch '1' is up, '0' is down swi_1 : in std_logic; -- switch '1' is up, '0' is down swi_2 : in std_logic; -- switch '1' is up, '0' is down swi_3 : in std_logic; -- switch '1' is up, '0' is down swi_4 : in std_logic; -- switch '1' is up, '0' is down swi_5 : in std_logic; -- switch '1' is up, '0' is down -- led_0 : out std_logic; -- LED: '1' to turn on; '0' to turn off led_1 : out std_logic; -- LED: '1' to turn on; '0' to turn off led_2 : out std_logic; -- LED: '1' to turn on; '0' to turn off led_3 : out std_logic; -- LED: '1' to turn on; '0' to turn off led_4 : out std_logic; -- LED: '1' to turn on; '0' to turn off led_5 : out std_logic -- LED: '1' to turn on; '0' to turn off ); attribute LOC : string; -- Pin Location attribute IOSTANDARD : string; -- LVTTL33, LVCMOS33 etc. attribute PERIOD : string; -- clock period attribute LOC of clk: signal is "Y9"; attribute IOSTANDARD of clk: signal is "LVCMOS33"; attribute PERIOD of clk: signal is "10 ns"; attribute LOC of swi_0: signal is "F22"; attribute IOSTANDARD of swi_0: signal is "LVCMOS33"; attribute LOC of swi_1: signal is "G22"; attribute IOSTANDARD of swi_1: signal is "LVCMOS33"; attribute LOC of swi_2: signal is "H22"; attribute IOSTANDARD of swi_2: signal is "LVCMOS33"; attribute LOC of swi_3: signal is "F21"; attribute IOSTANDARD of swi_3: signal is "LVCMOS33"; attribute LOC of swi_4: signal is "H19"; attribute IOSTANDARD of swi_4: signal is "LVCMOS33"; attribute LOC of swi_5: signal is "H18"; attribute IOSTANDARD of swi_5: signal is "LVCMOS33"; attribute LOC of led_0: signal is "T22"; attribute IOSTANDARD of led_0: signal is "LVCMOS33"; attribute LOC of led_1: signal is "T21"; attribute IOSTANDARD of led_1: signal is "LVCMOS33"; attribute LOC of led_2: signal is "U22"; attribute IOSTANDARD of led_2: signal is "LVCMOS33"; attribute LOC of led_3: signal is "U21"; attribute IOSTANDARD of led_3: signal is "LVCMOS33"; attribute LOC of led_4: signal is "V22"; attribute IOSTANDARD of led_4: signal is "LVCMOS33"; attribute LOC of led_5: signal is "W22"; attribute IOSTANDARD of led_5: signal is "LVCMOS33"; end entity top; architecture RTL of top is component DIVIDER generic ( RATIO : integer ); port ( clk_in : in std_logic; enable : in std_logic; -- clk_out : out std_logic ); end component divider; signal clkfb : std_logic; signal clk_0 : std_logic; signal clk_1 : std_logic; signal clk_2 : std_logic; signal clk_3 : std_logic; signal clk_4 : std_logic; signal clk_5 : std_logic; begin DIVIDER_0_inst : DIVIDER generic map ( RATIO => 10000000 ) port map ( clk_in => clk_0, enable => swi_0, clk_out => led_0); DIVIDER_1_inst : DIVIDER generic map ( RATIO => 10000000 ) port map ( clk_in => clk_1, enable => swi_1, clk_out => led_1); DIVIDER_2_inst : DIVIDER generic map ( RATIO => 10000000 ) port map ( clk_in => clk_2, enable => swi_2, clk_out => led_2); DIVIDER_3_inst : DIVIDER generic map ( RATIO => 10000000 ) port map ( clk_in => clk_3, enable => swi_3, clk_out => led_3); DIVIDER_4_inst : DIVIDER generic map ( RATIO => 10000000 ) port map ( clk_in => clk_4, enable => swi_4, clk_out => led_4); DIVIDER_5_inst : DIVIDER generic map ( RATIO => 10000000 ) port map ( clk_in => clk_5, enable => swi_5, clk_out => led_5); PLLE2_BASE_inst : PLLE2_BASE generic map ( BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW CLKFBOUT_MULT => 9, -- Multiply value for all CLKOUT, (2-64) CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000). CLKIN1_PERIOD => 10.0, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz). DIVCLK_DIVIDE => 1, -- Master division value, (1-56) REF_JITTER1 => 0.0, -- Reference input jitter in UI, (0.000-0.999). -- -- Divide amount for each CLKOUT (1-128) CLKOUT0_DIVIDE => 11, CLKOUT1_DIVIDE => 12, CLKOUT2_DIVIDE => 13, CLKOUT3_DIVIDE => 14, CLKOUT4_DIVIDE => 15, CLKOUT5_DIVIDE => 16, -- -- Duty cycle for each CLKOUT (0.001-0.999). CLKOUT0_DUTY_CYCLE => 0.5, CLKOUT1_DUTY_CYCLE => 0.5, CLKOUT2_DUTY_CYCLE => 0.5, CLKOUT3_DUTY_CYCLE => 0.5, CLKOUT4_DUTY_CYCLE => 0.5, CLKOUT5_DUTY_CYCLE => 0.5, -- -- Phase offset for each CLKOUT (-360.000-360.000). CLKOUT0_PHASE => 0.0, CLKOUT1_PHASE => 0.0, CLKOUT2_PHASE => 0.0, CLKOUT3_PHASE => 0.0, CLKOUT4_PHASE => 0.0, CLKOUT5_PHASE => 0.0, -- STARTUP_WAIT => "FALSE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE") ) port map ( CLKIN1 => clk, -- 1-bit input: Input clock PWRDWN => '0', -- 1-bit input: Power-down RST => '0', -- 1-bit input: Reset CLKFBIN => clkfb, -- 1-bit input: Feedback clock -- Clock Outputs: 1-bit (each) output: User configurable clock outputs CLKOUT0 => clk_0, CLKOUT1 => clk_1, CLKOUT2 => clk_2, CLKOUT3 => clk_3, CLKOUT4 => clk_4, CLKOUT5 => clk_5, CLKFBOUT => clkfb, -- 1-bit output: Feedback clock LOCKED => open -- 1-bit output: LOCK ); end RTL;