----------------------------------------------------------------------------
--  blink_divider.vhd
--	ZedBoard simple VHDL example
--	Version 1.0
--
--  Copyright (C) 2013 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
--
--  xflow -p xc7z020clg484-1 -synth xst_vhdl.opt blink_divider.vhd
--  xflow -p xc7z020clg484-1 -implement balanced.opt -config bitgen.opt blink_divider.ngc
--  promgen -w -b -p bin -o blink_divider.bin -u 0 blink_divider.bit -data_width 32
----------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;

entity divider is
    generic (
	RATIO : integer := 10000000
    );
    port (
	clk_in  : in std_logic;		-- input clock
	--
	enable  : in std_logic;		-- enable divider
	--
	clk_out : out std_logic		-- output clk_in
    );
end entity divider;

architecture RTL of divider is
begin
    divide_proc : process(clk_in, enable)
    variable count : integer range 0 to RATIO - 1;
    begin
	if enable = '0' then		-- reset
	    count := 0;
	elsif rising_edge(clk_in) then	-- clk
	    if count = RATIO - 1 then
	    	count := 0;
	    else
	    	count := count + 1;
	    end if;
	end if;
	
	if count < RATIO / 2 then
	    clk_out <= '0';
	else
	    clk_out <= '1';
	end if;
    end process;
end RTL;


library IEEE;
use IEEE.std_logic_1164.all;

Library UNISIM;
use UNISIM.vcomponents.all;

entity top is
    port (
	clk	: in std_logic;		-- input clock to FPGA
	--
	swi_0	: in std_logic;		-- switch '1' is up, '0' is down
	swi_1	: in std_logic;		-- switch '1' is up, '0' is down
	swi_2	: in std_logic;		-- switch '1' is up, '0' is down
	swi_3	: in std_logic;		-- switch '1' is up, '0' is down
	swi_4	: in std_logic;		-- switch '1' is up, '0' is down
	swi_5	: in std_logic;		-- switch '1' is up, '0' is down
	--
	led_0	: out std_logic;	-- LED: '1' to turn on; '0' to turn off
	led_1	: out std_logic;	-- LED: '1' to turn on; '0' to turn off
	led_2	: out std_logic;	-- LED: '1' to turn on; '0' to turn off
	led_3	: out std_logic;	-- LED: '1' to turn on; '0' to turn off
	led_4	: out std_logic;	-- LED: '1' to turn on; '0' to turn off
	led_5	: out std_logic 	-- LED: '1' to turn on; '0' to turn off
    );

    attribute LOC      : string;	-- Pin Location
    attribute IOSTANDARD : string;	-- LVTTL33, LVCMOS33 etc.
    attribute PERIOD : string;		-- clock period

    attribute LOC of clk: signal is "Y9";
    attribute IOSTANDARD of clk: signal is "LVCMOS33";
    attribute PERIOD of clk: signal is "10 ns";

    attribute LOC of swi_0: signal is "F22";
    attribute IOSTANDARD of swi_0: signal is "LVCMOS33";
    attribute LOC of swi_1: signal is "G22";
    attribute IOSTANDARD of swi_1: signal is "LVCMOS33";
    attribute LOC of swi_2: signal is "H22";
    attribute IOSTANDARD of swi_2: signal is "LVCMOS33";
    attribute LOC of swi_3: signal is "F21";
    attribute IOSTANDARD of swi_3: signal is "LVCMOS33";
    attribute LOC of swi_4: signal is "H19";
    attribute IOSTANDARD of swi_4: signal is "LVCMOS33";
    attribute LOC of swi_5: signal is "H18";
    attribute IOSTANDARD of swi_5: signal is "LVCMOS33";

    attribute LOC of led_0: signal is "T22";
    attribute IOSTANDARD of led_0: signal is "LVCMOS33";
    attribute LOC of led_1: signal is "T21";
    attribute IOSTANDARD of led_1: signal is "LVCMOS33";
    attribute LOC of led_2: signal is "U22";
    attribute IOSTANDARD of led_2: signal is "LVCMOS33";
    attribute LOC of led_3: signal is "U21";
    attribute IOSTANDARD of led_3: signal is "LVCMOS33";
    attribute LOC of led_4: signal is "V22";
    attribute IOSTANDARD of led_4: signal is "LVCMOS33";
    attribute LOC of led_5: signal is "W22";
    attribute IOSTANDARD of led_5: signal is "LVCMOS33";

end entity top;


architecture RTL of top is
    component DIVIDER
    	generic (
    	    RATIO : integer
    	);
    	port (
    	    clk_in  : in std_logic;
    	    enable  : in std_logic;
    	    --
    	    clk_out : out std_logic
    	);
    end component divider;
begin

    DIVIDER_0_inst : DIVIDER
    generic map ( RATIO => 10000000 )
    port map ( clk_in => clk, enable => swi_0, clk_out => led_0);

    DIVIDER_1_inst : DIVIDER
    generic map ( RATIO => 20000000 )
    port map ( clk_in => clk, enable => swi_1, clk_out => led_1);

    DIVIDER_2_inst : DIVIDER
    generic map ( RATIO => 30000000 )
    port map ( clk_in => clk, enable => swi_2, clk_out => led_2);

    DIVIDER_3_inst : DIVIDER
    generic map ( RATIO => 40000000 )
    port map ( clk_in => clk, enable => swi_3, clk_out => led_3);

    DIVIDER_4_inst : DIVIDER
    generic map ( RATIO => 50000000 )
    port map ( clk_in => clk, enable => swi_4, clk_out => led_4);

    DIVIDER_5_inst : DIVIDER
    generic map ( RATIO => 60000000 )
    port map ( clk_in => clk, enable => swi_5, clk_out => led_5);

end RTL;