----------------------------------------------------------------------------
--  blink.vhd
--	ZedBoard simple VHDL example
--	Version 1.0
--
--  Copyright (C) 2013 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
--
--  xflow -p xc7z020clg484-1 -synth xst_vhdl.opt blink.vhd
--  xflow -p xc7z020clg484-1 -implement balanced.opt -config bitgen.opt blink.ngc
--  promgen -w -b -p bin -o blink.bin -u 0 blink.bit -data_width 32
----------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;

entity top is
    port (
	clk	: in std_logic;		-- input clock to FPGA
	rst	: in std_logic;		-- reset input
	--
	led_0	: out std_logic		-- controls LED: '1' to turn on; '0' to turn off
    );

    attribute LOC      : string;	-- Pin Location
    attribute IOSTANDARD : string;	-- LVTTL33, LVCMOS33 etc.
    attribute PERIOD : string;		-- clock period

    attribute LOC of clk: signal is "Y9";
    attribute IOSTANDARD of clk: signal is "LVCMOS33";
    attribute PERIOD of clk: signal is "10 ns";

    attribute LOC of rst: signal is "P16";
    attribute IOSTANDARD of rst: signal is "LVCMOS33";

    attribute LOC of led_0: signal is "T22";
    attribute IOSTANDARD of led_0: signal is "LVCMOS33";

end entity top;

architecture RTL of top is
begin
    led_flash_proc : process(clk, rst)
    constant RATIO : integer := 100000000;
    variable count : integer range 0 to RATIO - 1;
    begin
	if rst = '1' then		-- reset
	    count := 0;
	elsif rising_edge(clk) then	-- clk
	    if count = RATIO - 1 then
	    	count := 0;
	    else
	    	count := count + 1;
	    end if;
	end if;
	
	if count < RATIO / 2 then
	    led_0 <= '0';
	else
	    led_0 <= '1';
	end if;
    end process;
end RTL;