;  Copyright (C) 2019 H.Poetzl
	;	
	;  This program is free software: you can redistribute it and/or
	;  modify it under the terms of the GNU General Public License
	;  as published by the Free Software Foundation, either version
	;  2 of the License, or (at your option) any later version.
	;

	PROCESSOR	16F1718
	RADIX		dec

	INCLUDE "p16f1718.inc"

	__config _CONFIG1, _FOSC_INTOSC & _WDTE_OFF & _MCLRE_ON & _BOREN_ON & _FCMEN_OFF
	__config _CONFIG2, _PLLEN_OFF & _ZCDDIS_OFF & _PPS1WAY_OFF

C1	EQU	0x70
C2	EQU	0x71
C3	EQU	0x72
C4	EQU	0x73

	; reset vector

	ORG __VECTOR_RESET
	PAGESEL init
	GOTO	init

	; interrupt vector

	ORG __VECTOR_INT

	BANKSEL INTCON
	BTFSS	INTCON,IOCIF
	BRA	_iocx

	BANKSEL	IOCBF
	MOVFW	IOCBF
	XORLW	0xFF
	ANDWF	IOCBF,F			; clear flag

	BANKSEL	PORTB
	MOVLW	'L'
	BTFSC	PORTB,6			; test input
	MOVLW	'H'
	CALL	chout

	INCF	C4
	
_iocx:	RETFIE


init:	BANKSEL	LATA
	MOVLW	00000111b
	MOVWF	LATA
	MOVLW	10000000b
	MOVWF	LATB
	MOVLW	00000000b
	MOVWF	LATC

	BANKSEL	TRISA
	MOVLW	11111000b	; RA0-RA2 out
	MOVWF	TRISA
	MOVLW	01111111b	; RB7 out
	MOVWF	TRISB
	MOVLW	01111110b	; RC0,RC7 out
	MOVWF	TRISC

	; setup Pin Properties

	BANKSEL	ANSELA
	CLRF	ANSELA
	CLRF	ANSELB
	CLRF	ANSELC

	BANKSEL	ODCONA
	MOVLW	00000111b	; RA0-RA2 od
	MOVWF	ODCONA
	CLRF	ODCONB
	CLRF	ODCONC

	BANKSEL WPUA
	MOVLW	11111000b	; RA3-RA7 up
	MOVWF	WPUA
	MOVLW	01111111b	; all but RB7
	MOVWF	WPUB
	MOVLW	01111110b	; RC1-RC6 up
	MOVWF	WPUC

	BANKSEL INLVLA
	MOVLW	11111111b	; all ST
	MOVWF	INLVLA
	MOVWF	INLVLB
	MOVWF	INLVLC

	BANKSEL OPTION_REG
	BCF	OPTION_REG,NOT_WPUEN

	; setup IOC

	BANKSEL	IOCAP
	CLRF	IOCAP
	CLRF	IOCAN

	MOVLW	01000000b	; RB6
	MOVWF	IOCBP
	MOVWF	IOCBN

	CLRF	IOCCP
	CLRF	IOCCN

	; setup PPS

	BANKSEL	PPSLOCK
	BCF	PPSLOCK, PPSLOCKED

	BANKSEL	RB7PPS
	MOVLW	10100b		; TX1
	MOVWF	RB7PPS

	; setup oscillator

	BANKSEL	OSCCON
	MOVLW	01111000b
	MOVWF	OSCCON

hfiofr:	BTFSS	OSCSTAT,HFIOFR
	GOTO	hfiofr		; wait for ready

hfiofl:	BTFSS   OSCSTAT,HFIOFL
	GOTO	hfiofl		; wait for lock

hfiofs:	BTFSS   OSCSTAT,HFIOFS
	GOTO	hfiofs		; wait for stable

	; setup UART1

	BANKSEL	TX1STA
	CLRF	TX1STA
	BSF	TX1STA,BRGH

	CLRF	RC1STA

	CLRF	BAUD1CON
	BSF	BAUD1CON,BRG16

	MOVLW	0x03
	MOVWF	SP1BRGL
	CLRF	SP1BRGH

	BSF	TX1STA,TXEN
	BSF	RC1STA,SPEN

	; enable IRQ

	BANKSEL	INTCON
	BSF	INTCON,IOCIE	; enable IOC IRQ
	BSF	INTCON,PEIE	; enable peripheral IRQ
	BSF	INTCON,GIE	; enable global IRQ

	goto	main


chout:	BANKSEL PIR1
choutl:	BTFSS	PIR1,TXIF
	GOTO	choutl

	BANKSEL	TX1REG
	MOVWF	TX1REG
	RETURN


main:	MOVLW	'P'
	CALL	chout
	MOVLW	'I'
	CALL	chout
	MOVLW	'C'
	CALL	chout
	MOVLW	'1'
	CALL	chout
	MOVLW	'6'
	CALL	chout
	MOVLW	'.'
	CALL	chout

	CLRF	C4

	BANKSEL LATA
loop:	MOVFW	C4
	MOVWF	LATA
	GOTO	loop

	end