----------------------------------------------------------------------------
--  prng.vhd
--	Pseudo Random Generators
--	Version 1.1
--
--  Copyright (C) 2014-2017 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
----------------------------------------------------------------------------

----------------------------------------------------------------------------
--  PRNG Entity Declaration
----------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;


entity prng is
    generic(
    	DATA_WIDTH : positive := 32;
	POLYNOMIAL : std_logic_vector := x"80200003";
	REG_RNG    : boolean := false );
    port(
	clk   : in std_logic;
	ce    : in std_logic;
	reset : in std_logic;
	shift : in std_logic;
	s_in  : in std_logic;
	s_out : out std_logic;
	rng   : out std_logic_vector (DATA_WIDTH-1 downto 0)
    );
end prng;

----------------------------------------------------------------------------
--  LFSR RNG (Fibonacci)
--	Version 1.2
--
----------------------------------------------------------------------------

architecture LFSR_FIB of prng is

    signal sr : std_logic_vector (DATA_WIDTH-1 downto 0)
	:= ( others => '0' );
    signal sr_d : std_logic_vector (DATA_WIDTH-1 downto 0)
        := ( others => '0' );
begin
    prng : process (clk)
	variable fb : std_logic;
    begin
	if rising_edge(clk) then
	    if reset then
	        sr <= (others => '0');
		sr_d <= (others => '0');
		
	    elsif ce then
		if shift then
		    s_out <= sr(DATA_WIDTH-1);
		    sr <= sr(DATA_WIDTH-2 downto 0) & s_in;

		else
		    fb := '0';
		    for I in DATA_WIDTH-1 downto 0 loop
			if POLYNOMIAL(DATA_WIDTH-I-1) then
			    fb := fb xor sr(I);
			end if;
		    end loop;

		    sr <= sr(DATA_WIDTH-2 downto 0) & not fb;
		end if;
		
		if REG_RNG then
		    sr_d <= sr;
		end if;
	    end if;
	end if;
    end process;

    rng <= sr_d when REG_RNG else sr;
end LFSR_FIB;

----------------------------------------------------------------------------
--  LFSR RNG (Galois)
--	Version 1.2
--
----------------------------------------------------------------------------

architecture LFSR_GAL of prng is

    signal sr : std_logic_vector (DATA_WIDTH-1 downto 0)
	:= ( others => '0' );
    signal sr_d : std_logic_vector (DATA_WIDTH-1 downto 0)
        := ( others => '0' );
begin
    prng : process (clk)
    	variable fb : std_logic_vector (DATA_WIDTH-1 downto 0);
    begin
	if rising_edge(clk) then
	    if reset then
	        sr <= (others => '0');
		sr_d <= (others => '0');
		
	    elsif ce then
		if shift then
		    s_out <= sr(DATA_WIDTH-1);
		    sr <= sr(DATA_WIDTH-2 downto 0) & s_in;

		else
		    fb := (others => '0');
		    for I in DATA_WIDTH-1 downto 0 loop
			if POLYNOMIAL(DATA_WIDTH-I-1) then
			    fb(I) := not sr(0);
			end if;
		    end loop;

		    sr <= ('1' & sr(DATA_WIDTH-1 downto 1)) xor fb;
		end if;
	    end if;
	end if;
    end process;

    rng <= sr;
end LFSR_GAL;