----------------------------------------------------------------------------
--  top.vhd
--	ZedBoard PMOD Clock Module (JA)
--	Version 1.0
--
--  Copyright (C) 2014 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
--
--  Vivado 2014.2:
--    mkdir -p build.vivado
--    (cd build.vivado && vivado -mode tcl -source ../vivado.tcl)
----------------------------------------------------------------------------



library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;

library unisim;
use unisim.VCOMPONENTS.ALL;

entity top is
    port (
	clk_100 : in std_logic;			-- input clock to FPGA
	--
	pmod_clock_sda : inout std_logic;
	pmod_clock_scl : inout std_logic;
	--
	pmod_clock_y : in std_logic_vector (3 downto 0);
	--
	pmod_clock_s : out std_logic_vector (1 downto 0);
	--
	swi : in std_logic_vector (7 downto 0);
	led : out std_logic_vector (7 downto 0)
    );

end entity top;


architecture RTL of top is

    attribute KEEP_HIERARCHY of RTL : architecture is "TRUE";

    --------------------------------------------------------------------
    -- I2C0 Signals
    --------------------------------------------------------------------

    signal i2c0_sda_i : std_ulogic;
    signal i2c0_sda_o : std_ulogic;
    signal i2c0_sda_t : std_ulogic;
    signal i2c0_sda_t_n : std_ulogic;

    signal i2c0_scl_i : std_ulogic;
    signal i2c0_scl_o : std_ulogic;
    signal i2c0_scl_t : std_ulogic;
    signal i2c0_scl_t_n : std_ulogic;

    --------------------------------------------------------------------
    -- Clock Signals
    --------------------------------------------------------------------

    signal clock : std_logic_vector (7 downto 0);

begin

    --------------------------------------------------------------------
    -- PS7 Interface
    --------------------------------------------------------------------

    ps7_stub_inst : entity work.ps7_stub
	port map (
	    i2c0_sda_i => i2c0_sda_i,
	    i2c0_sda_o => i2c0_sda_o,
	    i2c0_sda_t_n => i2c0_sda_t_n,
	    --
	    i2c0_scl_i => i2c0_scl_i,
	    i2c0_scl_o => i2c0_scl_o,
	    i2c0_scl_t_n => i2c0_scl_t_n );

    --------------------------------------------------------------------
    -- I2C bus #0
    --------------------------------------------------------------------

    i2c0_sda_t <= not i2c0_sda_t_n;

    IOBUF_sda_inst0 : IOBUF
	generic map (
	    IOSTANDARD => "LVCMOS33",
	    DRIVE => 4 )
	port map (
	    I => i2c0_sda_o, O => i2c0_sda_i,
	    T => i2c0_sda_t, IO => pmod_clock_sda );

    i2c0_scl_t <= not i2c0_scl_t_n;

    IOBUF_scl_inst0 : IOBUF
	generic map (
	    IOSTANDARD => "LVCMOS33",
	    DRIVE => 4 )
	port map (
	    I => i2c0_scl_o, O => i2c0_scl_i,
	    T => i2c0_scl_t, IO => pmod_clock_scl );

    --------------------------------------------------------------------
    -- PMOD Clock 906
    --------------------------------------------------------------------

    pmod_clock_s <= swi (1 downto 0);

    clock(3 downto 0) <= pmod_clock_y;
    clock(6 downto 4) <= (others => '0');

    clock(7) <= clk_100;

    --------------------------------------------------------------------
    -- Dividers
    --------------------------------------------------------------------

    DIV_GEN : for I in 7 downto 0 generate
    begin
	async_div_inst : entity work.async_div
	    generic map (
		STAGES => 28 )
	    port map (
		clk_in => clock(I),
		clk_out => led(I));
    end generate;


end RTL;