----------------------------------------------------------------------------
--  async_div.vhd
--	Asynchronous Binary Divider
--	Version 1.2
--
--  Copyright (C) 2013-2014 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
--
----------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.ALL;

library unisim;
use unisim.VCOMPONENTS.all;

use work.vivado_pkg.ALL;


entity async_div is
    generic (
	STAGES	: natural := 8
    );
    port (
	clk_in	: in std_logic;				-- input clock
	enable	: in std_logic		:= '1';		-- enable divider
	--
	clk_out	: out std_logic				-- output clock
    );

end entity async_div;


architecture RTL of async_div is

    signal stage : std_logic_vector(STAGES downto 0);

begin

    stage(0) <= clk_in;

    GEN_STAGE : for N in 1 to STAGES generate
    begin
	div_proc : process (stage(N - 1))
	begin
	    if rising_edge(stage(N - 1)) then
		if enable = '1' then
		    stage(N) <= not stage(N);
		end if;
	    end if;
	end process;
    end generate;

    clk_out <= stage(STAGES);

end RTL;