----------------------------------------------------------------------------
--  filter.vhd
--	Digital Filter for Uart
--	Version 1.0
--
--  Copyright (C) 2015 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
--
----------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.ALL;

library unisim;
use unisim.VCOMPONENTS.ALL;


entity uart_filter is
    generic (
	SAMPLE_COUNT : natural := 5 );
    port (
	clk : in std_logic;
	--
	ser_in : in std_logic;
	--
        ser_out : out std_logic );
end entity uart_filter;

architecture RTL of uart_filter is
begin

    filter_proc : process(clk, ser_in)
	constant sample_lo_c : natural := SAMPLE_COUNT*1/3;
	constant sample_hi_c : natural := SAMPLE_COUNT*2/3;

	variable shift_v : std_logic_vector(SAMPLE_COUNT downto 0)
	    := (others => '0');

	variable count_v : natural range 0 to SAMPLE_COUNT;

	variable out_v : std_logic := '1';
    begin
	if rising_edge(clk) then
	    shift_v := shift_v(SAMPLE_COUNT-1 downto 0) & ser_in;

	    count_v := 0;
	    for I in SAMPLE_COUNT-1 downto 0 loop
		if shift_v(I) = '1' then
		    count_v := count_v + 1;
		end if;
	    end loop;

	    if count_v > sample_hi_c then
		out_v := '1';
	    elsif count_v <= sample_lo_c then
		out_v := '0';
	    end if;
        end if;    

	ser_out <= out_v;
    end process;

end RTL;