---------------------------------------------------------------------------- -- top.vhd (for icsp_new) -- Axiom Beta ICSP reimplementation -- Version 1.0 -- -- Copyright (C) 2023 H.Poetzl -- -- This program is free software: you can redistribute it and/or -- modify it under the terms of the GNU General Public License -- as published by the Free Software Foundation, either version -- 2 of the License, or (at your option) any later version. -- -- Vivado 2023.1: -- mkdir -p build.vivado -- (cd build.vivado && vivado -mode tcl -source ../vivado.tcl) ---------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.ALL; use IEEE.numeric_std.ALL; library unisim; use unisim.VCOMPONENTS.ALL; library unimacro; use unimacro.VCOMPONENTS.ALL; use work.axi3m_pkg.ALL; -- AXI3 Master use work.axi3ml_pkg.ALL; -- AXI3 Lite Master use work.axi3s_pkg.ALL; -- AXI3 Slave use work.reduce_pkg.ALL; -- Logic Reduction use work.vivado_pkg.ALL; -- Vivado Attributes use work.helper_pkg.ALL; -- Helpers entity top is port ( i2c_scl : inout std_ulogic; i2c_sda : inout std_ulogic; -- scope : out std_logic_vector (3 downto 0) ); end entity top; architecture RTL of top is attribute KEEP_HIERARCHY of RTL : architecture is "TRUE"; signal clk_100 : std_logic; signal clk_50r : std_logic; signal clk_50 : std_logic; signal clk_10 : std_logic; -------------------------------------------------------------------- -- PS7 Signals -------------------------------------------------------------------- signal ps_fclk : std_logic_vector (3 downto 0); signal ps_reset_n : std_logic_vector (3 downto 0); signal irq_f2p : std_logic_vector (19 downto 0); signal irq_p2f : std_logic_vector (28 downto 0); -------------------------------------------------------------------- -- PS7 AXI CMV Master Signals -------------------------------------------------------------------- signal m_axi0_aclk : std_logic; signal m_axi0_areset_n : std_logic; signal m_axi0_ri : axi3m_read_in_r; signal m_axi0_ro : axi3m_read_out_r; signal m_axi0_wi : axi3m_write_in_r; signal m_axi0_wo : axi3m_write_out_r; signal m_axi0l_ri : axi3ml_read_in_r; signal m_axi0l_ro : axi3ml_read_out_r; signal m_axi0l_wi : axi3ml_write_in_r; signal m_axi0l_wo : axi3ml_write_out_r; signal m_axi0a_aclk : std_logic_vector (1 downto 0); signal m_axi0a_areset_n : std_logic_vector (1 downto 0); signal m_axi0a_ri : axi3ml_read_in_a(1 downto 0); signal m_axi0a_ro : axi3ml_read_out_a(1 downto 0); signal m_axi0a_wi : axi3ml_write_in_a(1 downto 0); signal m_axi0a_wo : axi3ml_write_out_a(1 downto 0); -------------------------------------------------------------------- -- PS7 AXI HDMI Master Signals -------------------------------------------------------------------- signal m_axi1_aclk : std_logic; signal m_axi1_areset_n : std_logic; signal m_axi1_ri : axi3m_read_in_r; signal m_axi1_ro : axi3m_read_out_r; signal m_axi1_wi : axi3m_write_in_r; signal m_axi1_wo : axi3m_write_out_r; signal m_axi1l_ri : axi3ml_read_in_r; signal m_axi1l_ro : axi3ml_read_out_r; signal m_axi1l_wi : axi3ml_write_in_r; signal m_axi1l_wo : axi3ml_write_out_r; signal m_axi1a_aclk : std_logic_vector (7 downto 0); signal m_axi1a_areset_n : std_logic_vector (7 downto 0); signal m_axi1a_ri : axi3ml_read_in_a(7 downto 0); signal m_axi1a_ro : axi3ml_read_out_a(7 downto 0); signal m_axi1a_wi : axi3ml_write_in_a(7 downto 0); signal m_axi1a_wo : axi3ml_write_out_a(7 downto 0); -------------------------------------------------------------------- -- PS7 EMIO GPIO Signals -------------------------------------------------------------------- signal emio_gpio_i : std_logic_vector(63 downto 0); signal emio_gpio_o : std_logic_vector(63 downto 0); signal emio_gpio_t_n : std_logic_vector(63 downto 0); -------------------------------------------------------------------- -- I2C0 Signals -------------------------------------------------------------------- signal i2c0_sda_i : std_ulogic; signal i2c0_sda_o : std_ulogic; signal i2c0_sda_t : std_ulogic; signal i2c0_sda_t_n : std_ulogic; signal i2c0_scl_i : std_ulogic; signal i2c0_scl_o : std_ulogic; signal i2c0_scl_t : std_ulogic; signal i2c0_scl_t_n : std_ulogic; -------------------------------------------------------------------- -- I2C1 Signals -------------------------------------------------------------------- signal i2c1_sda_i : std_ulogic; signal i2c1_sda_o : std_ulogic; signal i2c1_sda_t : std_ulogic; signal i2c1_sda_t_n : std_ulogic; signal i2c1_scl_i : std_ulogic; signal i2c1_scl_o : std_ulogic; signal i2c1_scl_t : std_ulogic; signal i2c1_scl_t_n : std_ulogic; -------------------------------------------------------------------- -- I2C ICSP Mix Signals -------------------------------------------------------------------- signal i2c_sda_i : std_ulogic; signal i2c_sda_o : std_ulogic; signal i2c_sda_t : std_ulogic; signal i2c_scl_i : std_ulogic; signal i2c_scl_o : std_ulogic; signal i2c_scl_t : std_ulogic; signal icsp_enable : std_ulogic; -------------------------------------------------------------------- -- ICSP Signals -------------------------------------------------------------------- signal icsp_clk_o : std_ulogic; signal icsp_clk_t : std_ulogic; signal icsp_dat_i : std_ulogic; signal icsp_dat_o : std_ulogic; signal icsp_dat_t : std_ulogic; signal icsp_dat_t_n : std_ulogic; -------------------------------------------------------------------- -- Exotic Stuff -------------------------------------------------------------------- signal led_done : std_logic; signal usr_access : std_logic_vector (31 downto 0); begin -------------------------------------------------------------------- -- PS7 Interface -------------------------------------------------------------------- ps7_stub_inst : entity work.ps7_stub port map ( i2c0_sda_i => i2c0_sda_i, i2c0_sda_o => i2c0_sda_o, i2c0_sda_t_n => i2c0_sda_t_n, -- i2c0_scl_i => i2c0_scl_i, i2c0_scl_o => i2c0_scl_o, i2c0_scl_t_n => i2c0_scl_t_n, -- i2c1_sda_i => i2c1_sda_i, i2c1_sda_o => i2c1_sda_o, i2c1_sda_t_n => i2c1_sda_t_n, -- i2c1_scl_i => i2c1_scl_i, i2c1_scl_o => i2c1_scl_o, i2c1_scl_t_n => i2c1_scl_t_n, -- ps_fclk => ps_fclk, ps_reset_n => ps_reset_n, -- irq_f2p => irq_f2p, irq_p2f => irq_p2f, -- emio_gpio_i => emio_gpio_i, emio_gpio_o => emio_gpio_o, emio_gpio_t_n => emio_gpio_t_n, -- m_axi0_aclk => m_axi0_aclk, m_axi0_areset_n => m_axi0_areset_n, -- m_axi0_arid => m_axi0_ro.arid, m_axi0_araddr => m_axi0_ro.araddr, m_axi0_arburst => m_axi0_ro.arburst, m_axi0_arlen => m_axi0_ro.arlen, m_axi0_arsize => m_axi0_ro.arsize, m_axi0_arprot => m_axi0_ro.arprot, m_axi0_arvalid => m_axi0_ro.arvalid, m_axi0_arready => m_axi0_ri.arready, -- m_axi0_rid => m_axi0_ri.rid, m_axi0_rdata => m_axi0_ri.rdata, m_axi0_rlast => m_axi0_ri.rlast, m_axi0_rresp => m_axi0_ri.rresp, m_axi0_rvalid => m_axi0_ri.rvalid, m_axi0_rready => m_axi0_ro.rready, -- m_axi0_awid => m_axi0_wo.awid, m_axi0_awaddr => m_axi0_wo.awaddr, m_axi0_awburst => m_axi0_wo.awburst, m_axi0_awlen => m_axi0_wo.awlen, m_axi0_awsize => m_axi0_wo.awsize, m_axi0_awprot => m_axi0_wo.awprot, m_axi0_awvalid => m_axi0_wo.awvalid, m_axi0_awready => m_axi0_wi.wready, -- m_axi0_wid => m_axi0_wo.wid, m_axi0_wdata => m_axi0_wo.wdata, m_axi0_wstrb => m_axi0_wo.wstrb, m_axi0_wlast => m_axi0_wo.wlast, m_axi0_wvalid => m_axi0_wo.wvalid, m_axi0_wready => m_axi0_wi.wready, -- m_axi0_bid => m_axi0_wi.bid, m_axi0_bresp => m_axi0_wi.bresp, m_axi0_bvalid => m_axi0_wi.bvalid, m_axi0_bready => m_axi0_wo.bready, -- m_axi1_aclk => m_axi1_aclk, m_axi1_areset_n => m_axi1_areset_n, -- m_axi1_arid => m_axi1_ro.arid, m_axi1_araddr => m_axi1_ro.araddr, m_axi1_arburst => m_axi1_ro.arburst, m_axi1_arlen => m_axi1_ro.arlen, m_axi1_arsize => m_axi1_ro.arsize, m_axi1_arprot => m_axi1_ro.arprot, m_axi1_arvalid => m_axi1_ro.arvalid, m_axi1_arready => m_axi1_ri.arready, -- m_axi1_rid => m_axi1_ri.rid, m_axi1_rdata => m_axi1_ri.rdata, m_axi1_rlast => m_axi1_ri.rlast, m_axi1_rresp => m_axi1_ri.rresp, m_axi1_rvalid => m_axi1_ri.rvalid, m_axi1_rready => m_axi1_ro.rready, -- m_axi1_awid => m_axi1_wo.awid, m_axi1_awaddr => m_axi1_wo.awaddr, m_axi1_awburst => m_axi1_wo.awburst, m_axi1_awlen => m_axi1_wo.awlen, m_axi1_awsize => m_axi1_wo.awsize, m_axi1_awprot => m_axi1_wo.awprot, m_axi1_awvalid => m_axi1_wo.awvalid, m_axi1_awready => m_axi1_wi.wready, -- m_axi1_wid => m_axi1_wo.wid, m_axi1_wdata => m_axi1_wo.wdata, m_axi1_wstrb => m_axi1_wo.wstrb, m_axi1_wlast => m_axi1_wo.wlast, m_axi1_wvalid => m_axi1_wo.wvalid, m_axi1_wready => m_axi1_wi.wready, -- m_axi1_bid => m_axi1_wi.bid, m_axi1_bresp => m_axi1_wi.bresp, m_axi1_bvalid => m_axi1_wi.bvalid, m_axi1_bready => m_axi1_wo.bready ); clk_100 <= ps_fclk(0); clk_10 <= ps_fclk(1); -------------------------------------------------------------------- -- I2C Interface AB -------------------------------------------------------------------- i2c_sda_o <= icsp_dat_o when icsp_enable else i2c1_sda_o; i2c_sda_t <= icsp_dat_t when icsp_enable else i2c1_sda_t; i2c1_sda_i <= '1' when icsp_enable else i2c_sda_i; icsp_dat_i <= i2c_sda_i when icsp_enable else '1'; i2c1_sda_t <= not i2c1_sda_t_n; IOBUF_sda_inst : IOBUF port map ( I => i2c_sda_o, O => i2c_sda_i, T => i2c_sda_t, IO => i2c_sda ); i2c_scl_o <= icsp_clk_o when icsp_enable else i2c1_scl_o; i2c_scl_t <= icsp_clk_t when icsp_enable else i2c1_scl_t; i2c1_scl_i <= '1' when icsp_enable else i2c_scl_i; i2c1_scl_t <= not i2c1_scl_t_n; PULLUP_sda_inst : PULLUP port map ( O => i2c_sda ); IOBUF_scl_inst : IOBUF port map ( I => i2c_scl_o, O => i2c_scl_i, T => i2c_scl_t, IO => i2c_scl ); PULLUP_scl_inst : PULLUP port map ( O => i2c_scl ); -------------------------------------------------------------------- -- Clock Divider -------------------------------------------------------------------- BUFR_inst : BUFR generic map ( BUFR_DIVIDE => "2" ) port map ( CE => '1', CLR => '0', I => clk_100, O => clk_50r ); BUFG_inst : BUFG port map ( I => clk_50r, O => clk_50 ); -------------------------------------------------------------------- -- AXI3 M0 Interconnect -------------------------------------------------------------------- axi_lite_inst0 : entity work.axi_lite port map ( s_axi_aclk => m_axi0_aclk, s_axi_areset_n => m_axi0_areset_n, s_axi_ro => m_axi0_ri, s_axi_ri => m_axi0_ro, s_axi_wo => m_axi0_wi, s_axi_wi => m_axi0_wo, m_axi_ro => m_axi0l_ro, m_axi_ri => m_axi0l_ri, m_axi_wo => m_axi0l_wo, m_axi_wi => m_axi0l_wi ); m_axi0_aclk <= clk_100; axi_split_inst0 : entity work.axi_split2 generic map ( SPLIT_BIT => 20 ) port map ( s_axi_aclk => m_axi0_aclk, s_axi_areset_n => m_axi0_areset_n, -- s_axi_ro => m_axi0l_ri, s_axi_ri => m_axi0l_ro, s_axi_wo => m_axi0l_wi, s_axi_wi => m_axi0l_wo, -- m_axi_aclk => m_axi0a_aclk, m_axi_areset_n => m_axi0a_areset_n, -- m_axi_ri => m_axi0a_ri, m_axi_ro => m_axi0a_ro, m_axi_wi => m_axi0a_wi, m_axi_wo => m_axi0a_wo ); -------------------------------------------------------------------- -- AXI3 M1 Interconnect -------------------------------------------------------------------- axi_lite_inst1 : entity work.axi_lite port map ( s_axi_aclk => m_axi1_aclk, s_axi_areset_n => m_axi1_areset_n, s_axi_ro => m_axi1_ri, s_axi_ri => m_axi1_ro, s_axi_wo => m_axi1_wi, s_axi_wi => m_axi1_wo, m_axi_ro => m_axi1l_ro, m_axi_ri => m_axi1l_ri, m_axi_wo => m_axi1l_wo, m_axi_wi => m_axi1l_wi ); m_axi1_aclk <= clk_50; axi_split_inst1 : entity work.axi_split8 generic map ( SPLIT_BIT0 => 20, SPLIT_BIT1 => 21, SPLIT_BIT2 => 22 ) port map ( s_axi_aclk => m_axi1_aclk, s_axi_areset_n => m_axi1_areset_n, -- s_axi_ro => m_axi1l_ri, s_axi_ri => m_axi1l_ro, s_axi_wo => m_axi1l_wi, s_axi_wi => m_axi1l_wo, -- m_axi_aclk => m_axi1a_aclk, m_axi_areset_n => m_axi1a_areset_n, -- m_axi_ri => m_axi1a_ri, m_axi_ro => m_axi1a_ro, m_axi_wi => m_axi1a_wi, m_axi_wo => m_axi1a_wo ); -------------------------------------------------------------------- -- ICSP Interface -------------------------------------------------------------------- reg_icsp_inst : entity work.reg_icsp port map ( s_axi_aclk => m_axi1a_aclk(6), s_axi_areset_n => m_axi1a_areset_n(6), -- s_axi_ro => m_axi1a_ri(6), s_axi_ri => m_axi1a_ro(6), s_axi_wo => m_axi1a_wi(6), s_axi_wi => m_axi1a_wo(6), -- icsp_clk_in => clk_10, -- icsp_enable => icsp_enable, -- icsp_clk_o => icsp_clk_o, icsp_clk_t => icsp_clk_t, -- icsp_dat_i => icsp_dat_i, icsp_dat_o => icsp_dat_o, icsp_dat_t => icsp_dat_t, -- debug => scope ); -------------------------------------------------------------------- -- Exotic Stuff -------------------------------------------------------------------- STARTUPE2_inst : STARTUPE2 generic map ( PROG_USR => "FALSE", -- Program event security feature. SIM_CCLK_FREQ => 0.0 ) -- Configuration Clock Frequency(ns) port map ( CFGCLK => open, -- 1-bit output: Configuration main clock output CFGMCLK => open, -- 1-bit output: Configuration internal oscillator clock output EOS => open, -- 1-bit output: Active high output signal indicating the End Of Startup. PREQ => open, -- 1-bit output: PROGRAM request to fabric output CLK => '0', -- 1-bit input: User start-up clock input GSR => '0', -- 1-bit input: Global Set/Reset input (GSR cannot be used for the port name) GTS => '0', -- 1-bit input: Global 3-state input (GTS cannot be used for the port name) KEYCLEARB => '0', -- 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM) PACK => '0', -- 1-bit input: PROGRAM acknowledge input USRCCLKO => '0', -- 1-bit input: User CCLK input USRCCLKTS => '0', -- 1-bit input: User CCLK 3-state enable input USRDONEO => '0', -- 1-bit input: User DONE pin output control USRDONETS => led_done ); -- 1-bit input: User DONE 3-state enable output USR_ACCESSE2_inst : USR_ACCESSE2 port map ( CFGCLK => open, -- 1-bit output: Configuration Clock output DATA => usr_access, -- 32-bit output: Configuration Data output DATAVALID => open ); -- 1-bit output: Active high data valid output end RTL;