----------------------------------------------------------------------------
--  enc_8b10b.vhd
--	Encode 8B10B Bitstream
--	Version 1.0
--
--  Copyright (C) 2014 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
----------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;

use work.vivado_pkg.ALL;	-- Vivado Attributes


entity enc_8b10b is
    port (
	clk	: in std_logic;
	--
	din	: in std_logic_vector (7 downto 0);
	--
	dout	: out std_logic_vector (9 downto 0)
    );
end entity enc_8b10b;


architecture RTL of enc_8b10b is

    attribute KEEP_HIERARCHY of RTL : architecture is "TRUE";

    signal rd : std_logic := '0';

    alias din_34 : std_logic_vector (2 downto 0)
	is din(7 downto 5);

    alias din_56 : std_logic_vector (4 downto 0)
	is din(4 downto 0);

    signal ain_p1 : std_logic_vector (3 downto 0);
    signal cin_p1 : std_logic_vector (1 downto 0);

    signal vde_p1 : std_logic := '0';
    signal vde_p2 : std_logic := '0';

    signal ade_p1 : std_logic := '0';
    signal ade_p2 : std_logic := '0';

    signal enc_34_p1 : std_logic_vector (6 downto 0);

    alias enc_34_word_p1 : std_logic_vector (3 downto 0)
	is enc_34_p1(3 downto 0);
    alias enc_34_dp_p1 : std_logic is enc_34_p1(4);
    alias enc_34_kn_p1 : std_logic is enc_34_p1(5);
    alias enc_34_a7_p1 : std_logic is enc_34_p1(6);

    signal enc_34_word_p2 : std_logic_vector (3 downto 0);

    signal enc_56_p1 : std_logic_vector (8 downto 0);

    alias enc_56_word_p1 : std_logic_vector (5 downto 0)
	is enc_56_p1(5 downto 0);
    alias enc_56_dp_p1 : std_logic is enc_56_p1(6);
    alias enc_56_na_p1 : std_logic is enc_56_p1(7);
    alias enc_56_pa_p1 : std_logic is enc_56_p1(8);

    signal enc_56_word_p2 : std_logic_vector (5 downto 0);

    signal enc_terc_p2 : std_logic_vector (9 downto 0);
    signal enc_ctrl_p2 : std_logic_vector (9 downto 0);

    alias enc_34_word : std_logic_vector (3 downto 0)
	is dout(9 downto 6);

    alias enc_56_word : std_logic_vector (5 downto 0)
	is dout(5 downto 0);

begin

    delay_proc : process (clk)
    begin
	if rising_edge(clk) then
	    vde_p1 <= vde;
	    vde_p2 <= vde_p1;

	    ain_p1 <= ain;
	    ade_p1 <= ade;
	    ade_p2 <= ade_p1;

	    cin_p1 <= cin;
	end if;
    end process;

    rd_proc : process (clk)
    begin
	if rising_edge(clk) then
	    if vde_p1 = '1' then
		rd <= rd xor enc_56_dp_p1 xor enc_34_dp_p1;
	    else
		rd <= '0';
	    end if;
	end if;
    end process;

    dout_proc : process (clk)
    begin
	if rising_edge(clk) then
	    dout(9) <= enc_34_word_p2(3);
	    dout(8) <= enc_56_word_p2(5);
	    dout(7 downto 5) <= enc_34_word_p2(2 downto 0);
	    dout(4 downto 0) <= enc_56_word_p2(4 downto 0);
	end if;
    end process;

    enc_34_proc : process (clk)
    begin
	if rising_edge(clk) then
	    case din_34 is
		when "000"  => enc_34_p1 <= '0' & '0' & '1' & "1101";
		when "001"  => enc_34_p1 <= '0' & '1' & '0' & "1001";
		when "010"  => enc_34_p1 <= '0' & '1' & '0' & "1010";
		when "011"  => enc_34_p1 <= '0' & '0' & '1' & "0011";
		when "100"  => enc_34_p1 <= '0' & '1' & '1' & "1011";
		when "101"  => enc_34_p1 <= '0' & '1' & '0' & "0101";
		when "110"  => enc_34_p1 <= '0' & '0' & '0' & "0110";
		when others => enc_34_p1 <= '1' & '0' & '1' & "0111";
	    end case;

	    if enc_34_a7_p1 = '1' and		-- alternate codes
		(rd xor enc_56_dp_p1) = '0' and
		enc_56_na_p1 = '1' then
		enc_34_word_p2 <= "1110";

	    elsif enc_34_a7_p1 = '1' and	-- alternate codes
		(rd xor enc_56_dp_p1) = '1' and
		enc_56_pa_p1 = '1' then
		enc_34_word_p2 <= "0001";

	    elsif enc_34_dp_p1 = '1' and	-- disparity codes
		(rd xor enc_56_dp_p1) = '1' then
		enc_34_word_p2 <= not enc_34_word_p1;

	    else
		enc_34_word_p2 <= enc_34_word_p1;
	    end if;

	end if;
    end process;

    enc_56_proc : process (clk)
    begin
	if rising_edge(clk) then
	    case din_56 is
		when "00000" => enc_56_p1 <= '0' & '0' & '1' & "111001";
		when "00001" => enc_56_p1 <= '0' & '0' & '1' & "101110";
		when "00010" => enc_56_p1 <= '0' & '0' & '1' & "101101";
		when "00011" => enc_56_p1 <= '0' & '0' & '0' & "100011";
		when "00100" => enc_56_p1 <= '0' & '0' & '1' & "101011";
		when "00101" => enc_56_p1 <= '0' & '0' & '0' & "100101";
		when "00110" => enc_56_p1 <= '0' & '0' & '0' & "100110";
		when "00111" => enc_56_p1 <= '0' & '0' & '1' & "000111";
		when "01000" => enc_56_p1 <= '0' & '0' & '1' & "100111";
		when "01001" => enc_56_p1 <= '0' & '0' & '0' & "101001";
		when "01010" => enc_56_p1 <= '0' & '0' & '0' & "101010";
		when "01011" => enc_56_p1 <= '1' & '0' & '0' & "001011";
		when "01100" => enc_56_p1 <= '0' & '0' & '0' & "101100";
		when "01101" => enc_56_p1 <= '1' & '0' & '0' & "001101";
		when "01110" => enc_56_p1 <= '1' & '0' & '0' & "001110";
		when "01111" => enc_56_p1 <= '0' & '0' & '1' & "111010";
		when "10000" => enc_56_p1 <= '0' & '0' & '1' & "110110";
		when "10001" => enc_56_p1 <= '0' & '1' & '0' & "110001";
		when "10010" => enc_56_p1 <= '0' & '1' & '0' & "110010";
		when "10011" => enc_56_p1 <= '0' & '0' & '0' & "010011";
		when "10100" => enc_56_p1 <= '0' & '1' & '0' & "110100";
		when "10101" => enc_56_p1 <= '0' & '0' & '0' & "010101";
		when "10110" => enc_56_p1 <= '0' & '0' & '0' & "010110";
		when "10111" => enc_56_p1 <= '0' & '0' & '1' & "010111";
		when "11000" => enc_56_p1 <= '0' & '0' & '1' & "110011";
		when "11001" => enc_56_p1 <= '0' & '0' & '0' & "011001";
		when "11010" => enc_56_p1 <= '0' & '0' & '0' & "011010";
		when "11011" => enc_56_p1 <= '0' & '0' & '1' & "011011";
		when "11100" => enc_56_p1 <= '0' & '0' & '0' & "011100";
		when "11101" => enc_56_p1 <= '0' & '0' & '1' & "011101";
		when "11110" => enc_56_p1 <= '0' & '0' & '1' & "011110";
		when others  => enc_56_p1 <= '0' & '0' & '1' & "110101";
	    end case;

	    if enc_56_dp_p1 = '1' and	-- disparity codes
		rd = '1' then		-- invert on +1
		enc_56_word_p2 <= not enc_56_word_p1;
	    else
		enc_56_word_p2 <= enc_56_word_p1;
	    end if;
	end if;
    end process;

end RTL;