----------------------------------------------------------------------------
--  addr_seq.vhd
--	Address Sequencer
--	Version 1.0
--
--  Copyright (C) 2022 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
--
----------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;

use work.vivado_pkg.ALL;	-- Vivado Attributes


entity addr_seq is
    generic (
	ACNT_WIDTH : natural := 12;
	ADDR_WIDTH : natural := 32 );
    port (
	clk	: in std_logic;		-- base clock
	reset	: in std_logic;		-- reset to first buffer
	load	: in std_logic;		-- load buffer address
	enable	: in std_logic;		-- enable address increment
	--
	acnt_init : in std_logic_vector (ACNT_WIDTH - 1 downto 0);
	addr_init : in std_logic_vector (ADDR_WIDTH - 1 downto 0);
	--
	acnt_cinc : in std_logic_vector (ACNT_WIDTH - 1 downto 0);
	addr_cinc : in std_logic_vector (ADDR_WIDTH - 1 downto 0);
	--
	acnt_rinc : in std_logic_vector (ACNT_WIDTH - 1 downto 0);
	addr_rinc : in std_logic_vector (ADDR_WIDTH - 1 downto 0);
	--
	pattern : in std_logic_vector (ADDR_WIDTH - 1 downto 0);
	--
	acnt	: out std_logic_vector (ACNT_WIDTH - 1 downto 0);
	addr	: out std_logic_vector (ADDR_WIDTH - 1 downto 0);
	--
	match	: out std_logic_vector (4 downto 0);
	empty	: out std_logic;
	done	: out std_logic
    );

end entity addr_seq;


architecture RTL of addr_seq is

    signal agen_load : std_logic;
    signal agen_enable : std_logic;

    signal acnt_init_lat : std_logic_vector (ACNT_WIDTH - 1 downto 0);
    signal addr_init_lat : std_logic_vector (ADDR_WIDTH - 1 downto 0);

    signal acnt_cinc_lat : std_logic_vector (ACNT_WIDTH - 1 downto 0);
    signal addr_cinc_lat : std_logic_vector (ADDR_WIDTH - 1 downto 0);

    signal acnt_rinc_lat : std_logic_vector (ACNT_WIDTH - 1 downto 0);
    signal addr_rinc_lat : std_logic_vector (ADDR_WIDTH - 1 downto 0);

    signal pattern_lat : std_logic_vector (ADDR_WIDTH - 1 downto 0);

begin

    agen_load <= load or reset;
    agen_enable <= (enable and not done) or match(0);

    reg_proc: process (all)
    begin
	if load = '1' then
	    acnt_init_lat <= acnt_init;
	    addr_init_lat <= addr_init;

	    acnt_cinc_lat <= acnt_cinc;
	    addr_cinc_lat <= addr_cinc;

	    acnt_rinc_lat <= acnt_rinc;
	    addr_rinc_lat <= addr_rinc;

	    pattern_lat <= pattern;
	end if;
    end process;

    addr_gen_inst : entity work.addr_gen
	generic map (
	    ACNT_WIDTH => ACNT_WIDTH,
	    ADDR_WIDTH => ADDR_WIDTH )
	port map (
	    clk => clk,
	    load => agen_load,
	    enable => agen_enable,
	    --
	    acnt_init => acnt_init_lat,
	    addr_init => addr_init_lat,
	    --
	    acnt_cinc => acnt_cinc_lat,
	    addr_cinc => addr_cinc_lat,
	    --
	    acnt_rinc => acnt_rinc_lat,
	    addr_rinc => addr_rinc_lat,
	    --
	    pattern => pattern_lat,
	    --
	    acnt => acnt,
	    addr => addr,
	    match => match );

    done <= match(3) and not match(1);
    empty <= match(0) or done;

end RTL;