Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2019.1.2 (lin64) Build 2615518 Fri Aug  9 15:53:29 MDT 2019
| Date         : Sat Sep 14 04:16:05 2019
| Host         : newhost running 64-bit Mageia 6
| Command      : report_utilization -hierarchical -file utilization.rpt
| Design       : top
| Device       : 7z020clg400-1
| Design State : Routed
--------------------------------------------------------------------------------------

Utilization Design Information

Table of Contents
-----------------
1. Utilization by Hierarchy

1. Utilization by Hierarchy
---------------------------

+--------------------------------------------+---------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
|                  Instance                  |              Module             | Total LUTs | Logic LUTs | LUTRAMs | SRLs |  FFs  | RAMB36 | RAMB18 | DSP48 Blocks |
+--------------------------------------------+---------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
| top                                        |                           (top) |       6039 |       5684 |       0 |  355 | 10540 |     33 |      2 |           28 |
|   (top)                                    |                           (top) |        573 |        272 |       0 |  301 |  1751 |      0 |      0 |            0 |
|   FIFO_data_inst                           |   unimacro_FIFO_DUALCLOCK_MACRO |          0 |          0 |       0 |    0 |     0 |      1 |      0 |            0 |
|   FIFO_hdmi_inst                           | unimacro_FIFO_DUALCLOCK_MACRO_0 |          0 |          0 |       0 |    0 |     0 |      1 |      0 |            0 |
|   GEN_FCNT[0].fcnt_div_inst                |                       async_div |         10 |         10 |       0 |    0 |    10 |      0 |      0 |            0 |
|   GEN_FCNT[1].fcnt_div_inst                |                     async_div_1 |         10 |         10 |       0 |    0 |    10 |      0 |      0 |            0 |
|   GEN_FCNT[2].fcnt_div_inst                |                     async_div_2 |         10 |         10 |       0 |    0 |    10 |      0 |      0 |            0 |
|   GEN_FCNT[3].fcnt_div_inst                |                     async_div_3 |         10 |         10 |       0 |    0 |    10 |      0 |      0 |            0 |
|   GEN_FCNT[4].fcnt_div_inst                |                     async_div_4 |         10 |         10 |       0 |    0 |    10 |      0 |      0 |            0 |
|   axi_lite_inst0                           |                        axi_lite |          0 |          0 |       0 |    0 |    12 |      0 |      0 |            0 |
|   axi_lite_inst1                           |                      axi_lite_5 |          6 |          6 |       0 |    0 |    12 |      0 |      0 |            0 |
|   axi_split_inst0                          |                      axi_split8 |         83 |         83 |       0 |    0 |    14 |      0 |      0 |            0 |
|   axi_split_inst1                          |                    axi_split8_6 |         87 |         87 |       0 |    0 |    14 |      0 |      0 |            0 |
|   axihp_reader_inst                        |                    axihp_reader |          9 |          9 |       0 |    0 |     6 |      0 |      0 |            0 |
|   axihp_writer_inst                        |                    axihp_writer |         17 |         16 |       0 |    1 |    11 |      0 |      0 |            0 |
|   ch4_delay_inst                           |      sync_delay__parameterized4 |          0 |          0 |       0 |    0 |   176 |      0 |      0 |            0 |
|   cmv_pll_inst                             |              cmv_pll_rtl_250mhz |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            0 |
|   delay_inst0                              |                      sync_delay |          0 |          0 |       0 |    0 |    36 |      0 |      0 |            0 |
|   delay_inst1                              |      sync_delay__parameterized0 |          0 |          0 |       0 |    0 |    48 |      0 |      0 |            0 |
|   delay_inst2                              |      sync_delay__parameterized1 |          0 |          0 |       0 |    0 |     3 |      0 |      0 |            0 |
|   delay_inst3                              |      sync_delay__parameterized2 |          0 |          0 |       0 |    0 |     5 |      0 |      0 |            0 |
|   fifo_chop_inst                           |             fifo_chop_rtl_shift |        338 |        338 |       0 |    0 |   397 |      0 |      0 |            0 |
|   fifo_reset_inst0                         |                      fifo_reset |         14 |         10 |       0 |    4 |    38 |      0 |      0 |            0 |
|   fifo_reset_inst1                         |                    fifo_reset_7 |         13 |          9 |       0 |    4 |    38 |      0 |      0 |            0 |
|   hdmi_pll_inst                            |                        hdmi_pll |         19 |         19 |       0 |    0 |    32 |      0 |      0 |            0 |
|     (hdmi_pll_inst)                        |                        hdmi_pll |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            0 |
|     reg_pll_inst                           |                         reg_pll |         19 |         19 |       0 |    0 |    32 |      0 |      0 |            0 |
|   hdmi_scan_inst                           |                       scan_hdmi |          5 |          5 |       0 |    0 |    36 |      0 |      0 |            7 |
|     (hdmi_scan_inst)                       |                       scan_hdmi |          3 |          3 |       0 |    0 |    36 |      0 |      0 |            0 |
|     DSP48E1_limit_inst                     |      dsp48_wrap__parameterized2 |          2 |          2 |       0 |    0 |     0 |      0 |      0 |            1 |
|     scan_comp_inst0                        |                    scan_comp__1 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            1 |
|       DSP48E1_comp_inst                    |   dsp48_wrap__parameterized2_15 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            1 |
|     scan_comp_inst1                        |                    scan_comp__2 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            1 |
|       DSP48E1_comp_inst                    |   dsp48_wrap__parameterized2_14 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            1 |
|     scan_comp_inst2                        |                    scan_comp__3 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            1 |
|       DSP48E1_comp_inst                    |   dsp48_wrap__parameterized2_13 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            1 |
|     scan_comp_inst3                        |                    scan_comp__4 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            1 |
|       DSP48E1_comp_inst                    |   dsp48_wrap__parameterized2_12 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            1 |
|     scan_comp_inst4                        |                    scan_comp__5 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            1 |
|       DSP48E1_comp_inst                    |   dsp48_wrap__parameterized2_11 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            1 |
|     scan_comp_inst5                        |                       scan_comp |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            1 |
|       DSP48E1_comp_inst                    |   dsp48_wrap__parameterized2_10 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            1 |
|   lvds_pll_inst                            |             lvds_pll_rtl_250mhz |          1 |          1 |       0 |    0 |     0 |      0 |      0 |            0 |
|   matrix_inst                              |                   color_mat_4x4 |         93 |         52 |       0 |   41 |    97 |      0 |      0 |           16 |
|     (matrix_inst)                          |                   color_mat_4x4 |         41 |          0 |       0 |   41 |    97 |      0 |      0 |            0 |
|     GEN_MATI[0].GEN_MATJ[0].DSP48E1_matrix |      dsp48_wrap__parameterized3 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            1 |
|     GEN_MATI[0].GEN_MATJ[1].DSP48E1_matrix |   dsp48_wrap__parameterized3_16 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            1 |
|     GEN_MATI[0].GEN_MATJ[2].DSP48E1_matrix |   dsp48_wrap__parameterized3_17 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            1 |
|     GEN_MATI[0].GEN_MATJ[3].DSP48E1_matrix |   dsp48_wrap__parameterized3_18 |         13 |         13 |       0 |    0 |     0 |      0 |      0 |            1 |
|     GEN_MATI[1].GEN_MATJ[0].DSP48E1_matrix |   dsp48_wrap__parameterized3_19 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            1 |
|     GEN_MATI[1].GEN_MATJ[1].DSP48E1_matrix |   dsp48_wrap__parameterized3_20 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            1 |
|     GEN_MATI[1].GEN_MATJ[2].DSP48E1_matrix |   dsp48_wrap__parameterized3_21 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            1 |
|     GEN_MATI[1].GEN_MATJ[3].DSP48E1_matrix |   dsp48_wrap__parameterized3_22 |         13 |         13 |       0 |    0 |     0 |      0 |      0 |            1 |
|     GEN_MATI[2].GEN_MATJ[0].DSP48E1_matrix |   dsp48_wrap__parameterized3_23 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            1 |
|     GEN_MATI[2].GEN_MATJ[1].DSP48E1_matrix |   dsp48_wrap__parameterized3_24 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            1 |
|     GEN_MATI[2].GEN_MATJ[2].DSP48E1_matrix |   dsp48_wrap__parameterized3_25 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            1 |
|     GEN_MATI[2].GEN_MATJ[3].DSP48E1_matrix |   dsp48_wrap__parameterized3_26 |         13 |         13 |       0 |    0 |     0 |      0 |      0 |            1 |
|     GEN_MATI[3].GEN_MATJ[0].DSP48E1_matrix |   dsp48_wrap__parameterized3_27 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            1 |
|     GEN_MATI[3].GEN_MATJ[1].DSP48E1_matrix |   dsp48_wrap__parameterized3_28 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            1 |
|     GEN_MATI[3].GEN_MATJ[2].DSP48E1_matrix |   dsp48_wrap__parameterized3_29 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            1 |
|     GEN_MATI[3].GEN_MATJ[3].DSP48E1_matrix |   dsp48_wrap__parameterized3_30 |         13 |         13 |       0 |    0 |     0 |      0 |      0 |            1 |
|   out_delay_inst                           |      sync_delay__parameterized5 |          3 |          3 |       0 |    0 |   240 |      0 |      0 |            0 |
|   par_match_inst                           |                       par_match |        231 |        231 |       0 |    0 |   264 |      0 |      0 |            0 |
|   pixel_remap_even_inst                    |                     pixel_remap |        657 |        654 |       0 |    3 |  1279 |      4 |      1 |            0 |
|     (pixel_remap_even_inst)                |                     pixel_remap |        540 |        537 |       0 |    3 |  1279 |      0 |      0 |            0 |
|     gen_all_mem[0].ram_data0               |  ram_sdp_reg__parameterized0_49 |         25 |         25 |       0 |    0 |     0 |      1 |      0 |            0 |
|     gen_all_mem[1].ram_data0               |  ram_sdp_reg__parameterized0_50 |         25 |         25 |       0 |    0 |     0 |      1 |      0 |            0 |
|     gen_all_mem[2].ram_data0               |  ram_sdp_reg__parameterized0_51 |         25 |         25 |       0 |    0 |     0 |      1 |      0 |            0 |
|     gen_all_mem[3].ram_data0               |  ram_sdp_reg__parameterized0_52 |         25 |         25 |       0 |    0 |     0 |      1 |      0 |            0 |
|     ram_sync0                              |                  ram_sdp_reg_53 |         17 |         17 |       0 |    0 |     0 |      0 |      1 |            0 |
|   pixel_remap_odd_inst                     |     pixel_remap__parameterized0 |        654 |        654 |       0 |    0 |  1276 |      4 |      1 |            0 |
|     (pixel_remap_odd_inst)                 |     pixel_remap__parameterized0 |        537 |        537 |       0 |    0 |  1276 |      0 |      0 |            0 |
|     gen_all_mem[0].ram_data0               |     ram_sdp_reg__parameterized0 |         25 |         25 |       0 |    0 |     0 |      1 |      0 |            0 |
|     gen_all_mem[1].ram_data0               |  ram_sdp_reg__parameterized0_31 |         25 |         25 |       0 |    0 |     0 |      1 |      0 |            0 |
|     gen_all_mem[2].ram_data0               |  ram_sdp_reg__parameterized0_32 |         25 |         25 |       0 |    0 |     0 |      1 |      0 |            0 |
|     gen_all_mem[3].ram_data0               |  ram_sdp_reg__parameterized0_33 |         25 |         25 |       0 |    0 |     0 |      1 |      0 |            0 |
|     ram_sync0                              |                     ram_sdp_reg |         17 |         17 |       0 |    0 |     0 |      0 |      1 |            0 |
|   ps7_stub_inst                            |                        ps7_stub |         17 |         17 |       0 |    0 |     0 |      0 |      0 |            0 |
|   raddr_gen_inst                           |                       addr_qbuf |        162 |        162 |       0 |    0 |    16 |      0 |      0 |            1 |
|     (raddr_gen_inst)                       |                       addr_qbuf |         71 |         71 |       0 |    0 |     2 |      0 |      0 |            0 |
|     addr_gen_inst                          |                        addr_gen |         91 |         91 |       0 |    0 |    14 |      0 |      0 |            1 |
|       (addr_gen_inst)                      |                        addr_gen |         25 |         25 |       0 |    0 |    14 |      0 |      0 |            0 |
|       DSP48_addr_inst                      |                    dsp48_wrap_9 |         66 |         66 |       0 |    0 |     0 |      0 |      0 |            1 |
|   rc_noise_inst                            |                   row_col_noise |         58 |         58 |       0 |    0 |     0 |      0 |      0 |            3 |
|     DSP48E1_ch0_ch1                        |      dsp48_wrap__parameterized1 |         24 |         24 |       0 |    0 |     0 |      0 |      0 |            1 |
|     DSP48E1_ch2_ch3                        |   dsp48_wrap__parameterized1_48 |         24 |         24 |       0 |    0 |     0 |      0 |      0 |            1 |
|     DSP48E1_row_col                        |      dsp48_wrap__parameterized0 |         10 |         10 |       0 |    0 |     0 |      0 |      0 |            1 |
|   reg_delay_inst                           |                       reg_delay |        227 |        227 |       0 |    0 |   152 |      0 |      0 |            0 |
|     (reg_delay_inst)                       |                       reg_delay |        221 |        221 |       0 |    0 |   104 |      0 |      0 |            0 |
|     pp_reg_sync_inst                       |     pp_reg_sync__parameterized0 |          6 |          6 |       0 |    0 |    48 |      0 |      0 |            0 |
|       (pp_reg_sync_inst)                   |     pp_reg_sync__parameterized0 |          6 |          6 |       0 |    0 |    44 |      0 |      0 |            0 |
|       SYNC_ping_inst                       |                    data_sync__1 |          0 |          0 |       0 |    0 |     2 |      0 |      0 |            0 |
|       SYNC_pong_inst                       |                    data_sync__2 |          0 |          0 |       0 |    0 |     2 |      0 |      0 |            0 |
|   reg_file_inst0                           |                        reg_file |        328 |        328 |       0 |    0 |   565 |      0 |      0 |            0 |
|   reg_file_inst1                           |        reg_file__parameterized1 |        299 |        299 |       0 |    0 |   629 |      0 |      0 |            0 |
|   reg_file_inst2                           |        reg_file__parameterized2 |        261 |        261 |       0 |    0 |   564 |      0 |      0 |            0 |
|   reg_file_inst3                           |        reg_file__parameterized3 |        480 |        480 |       0 |    0 |  1204 |      0 |      0 |            0 |
|   reg_file_inst4                           |        reg_file__parameterized0 |        151 |        151 |       0 |    0 |   116 |      0 |      0 |            0 |
|   reg_lut_inst0                            |                   reg_lut_11x12 |        117 |        117 |       0 |    0 |   123 |      6 |      0 |            0 |
|     reg_lutn_inst                          |        reg_lutn__parameterized0 |        117 |        117 |       0 |    0 |   123 |      6 |      0 |            0 |
|       (reg_lutn_inst)                      |        reg_lutn__parameterized0 |         69 |         69 |       0 |    0 |    45 |      0 |      0 |            0 |
|       GEN_LUT[0].bram_lut_inst             |     bram_lut__parameterized0__1 |          8 |          8 |       0 |    0 |    13 |      1 |      0 |            0 |
|       GEN_LUT[1].bram_lut_inst             |     bram_lut__parameterized0__2 |          8 |          8 |       0 |    0 |    13 |      1 |      0 |            0 |
|       GEN_LUT[2].bram_lut_inst             |     bram_lut__parameterized0__3 |          8 |          8 |       0 |    0 |    13 |      1 |      0 |            0 |
|       GEN_LUT[3].bram_lut_inst             |     bram_lut__parameterized0__4 |          8 |          8 |       0 |    0 |    13 |      1 |      0 |            0 |
|       GEN_LUT[4].bram_lut_inst             |     bram_lut__parameterized0__5 |          8 |          8 |       0 |    0 |    13 |      1 |      0 |            0 |
|       GEN_LUT[5].bram_lut_inst             |        bram_lut__parameterized0 |          8 |          8 |       0 |    0 |    13 |      1 |      0 |            0 |
|   reg_lut_inst1                            |                   reg_lut_12x16 |        124 |        124 |       0 |    0 |   113 |      8 |      0 |            0 |
|     reg_lutn_inst                          |        reg_lutn__parameterized1 |        124 |        124 |       0 |    0 |   113 |      8 |      0 |            0 |
|       (reg_lutn_inst)                      |        reg_lutn__parameterized1 |         52 |         52 |       0 |    0 |    45 |      0 |      0 |            0 |
|       GEN_LUT[0].bram_lut_inst             |     bram_lut__parameterized1__1 |         19 |         19 |       0 |    0 |    17 |      2 |      0 |            0 |
|       GEN_LUT[1].bram_lut_inst             |     bram_lut__parameterized1__2 |         19 |         19 |       0 |    0 |    17 |      2 |      0 |            0 |
|       GEN_LUT[2].bram_lut_inst             |     bram_lut__parameterized1__3 |         17 |         17 |       0 |    0 |    17 |      2 |      0 |            0 |
|       GEN_LUT[3].bram_lut_inst             |        bram_lut__parameterized1 |         17 |         17 |       0 |    0 |    17 |      2 |      0 |            0 |
|   reg_lut_inst2                            |                   reg_lut_12x18 |        102 |        102 |       0 |    0 |   123 |      8 |      0 |            0 |
|     reg_lutn_inst                          |                        reg_lutn |        102 |        102 |       0 |    0 |   123 |      8 |      0 |            0 |
|       (reg_lutn_inst)                      |                        reg_lutn |         54 |         54 |       0 |    0 |    47 |      0 |      0 |            0 |
|       GEN_LUT[0].bram_lut_inst             |                     bram_lut__1 |         12 |         12 |       0 |    0 |    19 |      2 |      0 |            0 |
|       GEN_LUT[1].bram_lut_inst             |                     bram_lut__2 |         12 |         12 |       0 |    0 |    19 |      2 |      0 |            0 |
|       GEN_LUT[2].bram_lut_inst             |                     bram_lut__3 |         12 |         12 |       0 |    0 |    19 |      2 |      0 |            0 |
|       GEN_LUT[3].bram_lut_inst             |                        bram_lut |         12 |         12 |       0 |    0 |    19 |      2 |      0 |            0 |
|   reg_mem_inst                             |                         reg_mem |         31 |         31 |       0 |    0 |    40 |      1 |      0 |            0 |
|     (reg_mem_inst)                         |                         reg_mem |         24 |         24 |       0 |    0 |    30 |      0 |      0 |            0 |
|     bram_lut_inst                          |        bram_lut__parameterized2 |          7 |          7 |       0 |    0 |    10 |      1 |      0 |            0 |
|   reg_spi_inst                             |                         reg_spi |         44 |         43 |       0 |    1 |   152 |      0 |      0 |            0 |
|     (reg_spi_inst)                         |                         reg_spi |         20 |         20 |       0 |    0 |    36 |      0 |      0 |            0 |
|     pp_reg_sync_inst                       |                     pp_reg_sync |          6 |          6 |       0 |    0 |    88 |      0 |      0 |            0 |
|       (pp_reg_sync_inst)                   |                     pp_reg_sync |          6 |          6 |       0 |    0 |    84 |      0 |      0 |            0 |
|       SYNC_ping_inst                       |                    data_sync__3 |          0 |          0 |       0 |    0 |     2 |      0 |      0 |            0 |
|       SYNC_pong_inst                       |                       data_sync |          0 |          0 |       0 |    0 |     2 |      0 |      0 |            0 |
|     spi_inst                               |                         cmv_spi |         18 |         17 |       0 |    1 |    28 |      0 |      0 |            0 |
|   rgb_hdmi_inst0                           |                        rgb_hdmi |        212 |        212 |       0 |    0 |   159 |      0 |      0 |            0 |
|     (rgb_hdmi_inst0)                       |                        rgb_hdmi |         38 |         38 |       0 |    0 |    78 |      0 |      0 |            0 |
|     ENC_GEN[0].enc_ctrl_inst               |                        enc_ctrl |          1 |          1 |       0 |    0 |     3 |      0 |      0 |            0 |
|     ENC_GEN[0].enc_terc_inst               |                        enc_terc |          5 |          5 |       0 |    0 |    10 |      0 |      0 |            0 |
|     ENC_GEN[0].enc_tmds_inst               |                    enc_tmds_rtl |         52 |         52 |       0 |    0 |    14 |      0 |      0 |            0 |
|     ENC_GEN[1].enc_ctrl_inst               |                     enc_ctrl__5 |          1 |          1 |       0 |    0 |     3 |      0 |      0 |            0 |
|     ENC_GEN[1].enc_terc_inst               |                     enc_terc__5 |          5 |          5 |       0 |    0 |    10 |      0 |      0 |            0 |
|     ENC_GEN[1].enc_tmds_inst               |                 enc_tmds_rtl__5 |         52 |         52 |       0 |    0 |    14 |      0 |      0 |            0 |
|     ENC_GEN[2].enc_ctrl_inst               |                     enc_ctrl__4 |          1 |          1 |       0 |    0 |     3 |      0 |      0 |            0 |
|     ENC_GEN[2].enc_terc_inst               |                     enc_terc__4 |          5 |          5 |       0 |    0 |    10 |      0 |      0 |            0 |
|     ENC_GEN[2].enc_tmds_inst               |                 enc_tmds_rtl__4 |         52 |         52 |       0 |    0 |    14 |      0 |      0 |            0 |
|     OSERDES_GEN[0].OSERDES_master_inst     |                 oserdes_wrap_40 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            0 |
|     OSERDES_GEN[0].OSERDES_slave_inst      | oserdes_wrap__parameterized0_41 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            0 |
|     OSERDES_GEN[1].OSERDES_master_inst     |                 oserdes_wrap_42 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            0 |
|     OSERDES_GEN[1].OSERDES_slave_inst      | oserdes_wrap__parameterized0_43 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            0 |
|     OSERDES_GEN[2].OSERDES_master_inst     |                 oserdes_wrap_44 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            0 |
|     OSERDES_GEN[2].OSERDES_slave_inst      | oserdes_wrap__parameterized0_45 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            0 |
|     OSERDES_GEN[3].OSERDES_master_inst     |                 oserdes_wrap_46 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            0 |
|     OSERDES_GEN[3].OSERDES_slave_inst      | oserdes_wrap__parameterized0_47 |          0 |          0 |       0 |    0 |     0 |      0 |      0 |            0 |
|   rgb_hdmi_inst1                           |        rgb_hdmi__parameterized0 |        252 |        252 |       0 |    0 |   159 |      0 |      0 |            0 |
|     (rgb_hdmi_inst1)                       |        rgb_hdmi__parameterized0 |         38 |         38 |       0 |    0 |    78 |      0 |      0 |            0 |
|     ENC_GEN[0].enc_ctrl_inst               |                     enc_ctrl__3 |          1 |          1 |       0 |    0 |     3 |      0 |      0 |            0 |
|     ENC_GEN[0].enc_terc_inst               |                     enc_terc__3 |          5 |          5 |       0 |    0 |    10 |      0 |      0 |            0 |
|     ENC_GEN[0].enc_tmds_inst               |                 enc_tmds_rtl__3 |         52 |         52 |       0 |    0 |    14 |      0 |      0 |            0 |
|     ENC_GEN[1].enc_ctrl_inst               |                     enc_ctrl__2 |          1 |          1 |       0 |    0 |     3 |      0 |      0 |            0 |
|     ENC_GEN[1].enc_terc_inst               |                     enc_terc__2 |          5 |          5 |       0 |    0 |    10 |      0 |      0 |            0 |
|     ENC_GEN[1].enc_tmds_inst               |                 enc_tmds_rtl__2 |         52 |         52 |       0 |    0 |    14 |      0 |      0 |            0 |
|     ENC_GEN[2].enc_ctrl_inst               |                     enc_ctrl__1 |          1 |          1 |       0 |    0 |     3 |      0 |      0 |            0 |
|     ENC_GEN[2].enc_terc_inst               |                     enc_terc__1 |          5 |          5 |       0 |    0 |    10 |      0 |      0 |            0 |
|     ENC_GEN[2].enc_tmds_inst               |                 enc_tmds_rtl__1 |         52 |         52 |       0 |    0 |    14 |      0 |      0 |            0 |
|     OSERDES_GEN[0].OSERDES_master_inst     |                    oserdes_wrap |          8 |          8 |       0 |    0 |     0 |      0 |      0 |            0 |
|     OSERDES_GEN[0].OSERDES_slave_inst      |    oserdes_wrap__parameterized0 |          2 |          2 |       0 |    0 |     0 |      0 |      0 |            0 |
|     OSERDES_GEN[1].OSERDES_master_inst     |                 oserdes_wrap_34 |          8 |          8 |       0 |    0 |     0 |      0 |      0 |            0 |
|     OSERDES_GEN[1].OSERDES_slave_inst      | oserdes_wrap__parameterized0_35 |          2 |          2 |       0 |    0 |     0 |      0 |      0 |            0 |
|     OSERDES_GEN[2].OSERDES_master_inst     |                 oserdes_wrap_36 |          8 |          8 |       0 |    0 |     0 |      0 |      0 |            0 |
|     OSERDES_GEN[2].OSERDES_slave_inst      | oserdes_wrap__parameterized0_37 |          2 |          2 |       0 |    0 |     0 |      0 |      0 |            0 |
|     OSERDES_GEN[3].OSERDES_master_inst     |                 oserdes_wrap_38 |          8 |          8 |       0 |    0 |     0 |      0 |      0 |            0 |
|     OSERDES_GEN[3].OSERDES_slave_inst      | oserdes_wrap__parameterized0_39 |          2 |          2 |       0 |    0 |     0 |      0 |      0 |            0 |
|   scan_event_inst                          |                      scan_event |         81 |         81 |       0 |    0 |    50 |      0 |      0 |            0 |
|   ser_to_par_inst                          |                      ser_to_par |         67 |         67 |       0 |    0 |   464 |      0 |      0 |            0 |
|     (ser_to_par_inst)                      |                      ser_to_par |          1 |          1 |       0 |    0 |     2 |      0 |      0 |            0 |
|     GEN_serdes[0].serdes_inst              |                      cmv_serdes |          2 |          2 |       0 |    0 |    14 |      0 |      0 |            0 |
|     GEN_serdes[10].serdes_inst             |                  cmv_serdes__23 |          2 |          2 |       0 |    0 |    14 |      0 |      0 |            0 |
|     GEN_serdes[11].serdes_inst             |                  cmv_serdes__22 |          2 |          2 |       0 |    0 |    14 |      0 |      0 |            0 |
|     GEN_serdes[12].serdes_inst             |                  cmv_serdes__21 |          2 |          2 |       0 |    0 |    14 |      0 |      0 |            0 |
|     GEN_serdes[13].serdes_inst             |                  cmv_serdes__20 |          2 |          2 |       0 |    0 |    14 |      0 |      0 |            0 |
|     GEN_serdes[14].serdes_inst             |                  cmv_serdes__19 |          2 |          2 |       0 |    0 |    14 |      0 |      0 |            0 |
|     GEN_serdes[15].serdes_inst             |                  cmv_serdes__18 |          2 |          2 |       0 |    0 |    14 |      0 |      0 |            0 |
|     GEN_serdes[16].serdes_inst             |                  cmv_serdes__17 |          2 |          2 |       0 |    0 |    14 |      0 |      0 |            0 |
|     GEN_serdes[17].serdes_inst             |                  cmv_serdes__16 |          2 |          2 |       0 |    0 |    14 |      0 |      0 |            0 |
|     GEN_serdes[18].serdes_inst             |                  cmv_serdes__15 |          2 |          2 |       0 |    0 |    14 |      0 |      0 |            0 |
|     GEN_serdes[19].serdes_inst             |                  cmv_serdes__14 |          2 |          2 |       0 |    0 |    14 |      0 |      0 |            0 |
|     GEN_serdes[1].serdes_inst              |                  cmv_serdes__32 |          2 |          2 |       0 |    0 |    14 |      0 |      0 |            0 |
|     GEN_serdes[20].serdes_inst             |                  cmv_serdes__13 |          2 |          2 |       0 |    0 |    14 |      0 |      0 |            0 |
|     GEN_serdes[21].serdes_inst             |                  cmv_serdes__12 |          2 |          2 |       0 |    0 |    14 |      0 |      0 |            0 |
|     GEN_serdes[22].serdes_inst             |                  cmv_serdes__11 |          2 |          2 |       0 |    0 |    14 |      0 |      0 |            0 |
|     GEN_serdes[23].serdes_inst             |                  cmv_serdes__10 |          2 |          2 |       0 |    0 |    14 |      0 |      0 |            0 |
|     GEN_serdes[24].serdes_inst             |                   cmv_serdes__9 |          2 |          2 |       0 |    0 |    14 |      0 |      0 |            0 |
|     GEN_serdes[25].serdes_inst             |                   cmv_serdes__8 |          2 |          2 |       0 |    0 |    14 |      0 |      0 |            0 |
|     GEN_serdes[26].serdes_inst             |                   cmv_serdes__7 |          2 |          2 |       0 |    0 |    14 |      0 |      0 |            0 |
|     GEN_serdes[27].serdes_inst             |                   cmv_serdes__6 |          2 |          2 |       0 |    0 |    14 |      0 |      0 |            0 |
|     GEN_serdes[28].serdes_inst             |                   cmv_serdes__5 |          2 |          2 |       0 |    0 |    14 |      0 |      0 |            0 |
|     GEN_serdes[29].serdes_inst             |                   cmv_serdes__4 |          2 |          2 |       0 |    0 |    14 |      0 |      0 |            0 |
|     GEN_serdes[2].serdes_inst              |                  cmv_serdes__31 |          2 |          2 |       0 |    0 |    14 |      0 |      0 |            0 |
|     GEN_serdes[30].serdes_inst             |                   cmv_serdes__3 |          2 |          2 |       0 |    0 |    14 |      0 |      0 |            0 |
|     GEN_serdes[31].serdes_inst             |                   cmv_serdes__2 |          2 |          2 |       0 |    0 |    14 |      0 |      0 |            0 |
|     GEN_serdes[32].serdes_inst             |                   cmv_serdes__1 |          2 |          2 |       0 |    0 |    14 |      0 |      0 |            0 |
|     GEN_serdes[3].serdes_inst              |                  cmv_serdes__30 |          2 |          2 |       0 |    0 |    14 |      0 |      0 |            0 |
|     GEN_serdes[4].serdes_inst              |                  cmv_serdes__29 |          2 |          2 |       0 |    0 |    14 |      0 |      0 |            0 |
|     GEN_serdes[5].serdes_inst              |                  cmv_serdes__28 |          2 |          2 |       0 |    0 |    14 |      0 |      0 |            0 |
|     GEN_serdes[6].serdes_inst              |                  cmv_serdes__27 |          2 |          2 |       0 |    0 |    14 |      0 |      0 |            0 |
|     GEN_serdes[7].serdes_inst              |                  cmv_serdes__26 |          2 |          2 |       0 |    0 |    14 |      0 |      0 |            0 |
|     GEN_serdes[8].serdes_inst              |                  cmv_serdes__25 |          2 |          2 |       0 |    0 |    14 |      0 |      0 |            0 |
|     GEN_serdes[9].serdes_inst              |                  cmv_serdes__24 |          2 |          2 |       0 |    0 |    14 |      0 |      0 |            0 |
|   sync_arm_inst                            |      pulse_sync__parameterized0 |          1 |          1 |       0 |    0 |     4 |      0 |      0 |            0 |
|   sync_done_inst                           |                      pulse_sync |          1 |          1 |       0 |    0 |     4 |      0 |      0 |            0 |
|   sync_frmreq_inst0                        |   pulse_sync__parameterized1__5 |          1 |          1 |       0 |    0 |     4 |      0 |      0 |            0 |
|   sync_rblock_inst                         |       data_sync__parameterized0 |          0 |          0 |       0 |    0 |     2 |      0 |      0 |            0 |
|   sync_rbuf_sel_inst                       |      sync_delay__parameterized3 |          0 |          0 |       0 |    0 |     4 |      0 |      0 |            0 |
|   sync_rload_inst                          |   pulse_sync__parameterized1__9 |          1 |          1 |       0 |    0 |     4 |      0 |      0 |            0 |
|   sync_rreset_inst                         |      pulse_sync__parameterized1 |          1 |          1 |       0 |    0 |     4 |      0 |      0 |            0 |
|   sync_rswitch_inst0                       |   pulse_sync__parameterized1__8 |          1 |          1 |       0 |    0 |     4 |      0 |      0 |            0 |
|   sync_rswitch_inst1                       |   pulse_sync__parameterized1__7 |          1 |          1 |       0 |    0 |     4 |      0 |      0 |            0 |
|   sync_wblock_inst                         |    data_sync__parameterized0__1 |          0 |          0 |       0 |    0 |     2 |      0 |      0 |            0 |
|   sync_wbuf_sel_inst                       |   sync_delay__parameterized3__1 |          0 |          0 |       0 |    0 |     4 |      0 |      0 |            0 |
|   sync_wempty_inst                         |    data_sync__parameterized0__2 |          0 |          0 |       0 |    0 |     2 |      0 |      0 |            0 |
|   sync_winact_inst                         |    data_sync__parameterized0__3 |          0 |          0 |       0 |    0 |     2 |      0 |      0 |            0 |
|   sync_wload_inst                          |   pulse_sync__parameterized1__2 |          1 |          1 |       0 |    0 |     4 |      0 |      0 |            0 |
|   sync_wreset_inst                         |   pulse_sync__parameterized1__1 |          1 |          1 |       0 |    0 |     4 |      0 |      0 |            0 |
|   sync_wswitch_inst0                       |   pulse_sync__parameterized1__3 |          1 |          1 |       0 |    0 |     4 |      0 |      0 |            0 |
|   sync_wswitch_inst1                       |   pulse_sync__parameterized1__4 |          1 |          1 |       0 |    0 |     4 |      0 |      0 |            0 |
|   waddr_gen_inst                           |                     addr_qbuf_8 |        162 |        162 |       0 |    0 |    16 |      0 |      0 |            1 |
|     (waddr_gen_inst)                       |                     addr_qbuf_8 |         71 |         71 |       0 |    0 |     2 |      0 |      0 |            0 |
|     addr_gen_inst                          |                     addr_gen__1 |         91 |         91 |       0 |    0 |    14 |      0 |      0 |            1 |
|       (addr_gen_inst)                      |                     addr_gen__1 |         25 |         25 |       0 |    0 |    14 |      0 |      0 |            0 |
|       DSP48_addr_inst                      |                      dsp48_wrap |         66 |         66 |       0 |    0 |     0 |      0 |      0 |            1 |
+--------------------------------------------+---------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
* Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining


Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.1.2 (lin64) Build 2615518 Fri Aug  9 15:53:29 MDT 2019
| Date         : Sat Sep 14 04:16:06 2019
| Host         : newhost running 64-bit Mageia 6
| Command      : report_clock_utilization -file utilization.rpt -append
| Design       : top
| Device       : 7z020-clg400
| Speed File   : -1  PRODUCTION 1.11 2014-09-11
| Design State : Routed
--------------------------------------------------------------------------------------

Clock Utilization Report

Table of Contents
-----------------
1. Clock Primitive Utilization
2. Global Clock Resources
3. Global Clock Source Details
4. Local Clock Details
5. Clock Regions: Key Resource Utilization
6. Clock Regions : Global Clock Summary
7. Device Cell Placement Summary for Global Clock g0
8. Device Cell Placement Summary for Global Clock g1
9. Device Cell Placement Summary for Global Clock g2
10. Device Cell Placement Summary for Global Clock g3
11. Device Cell Placement Summary for Global Clock g4
12. Device Cell Placement Summary for Global Clock g5
13. Device Cell Placement Summary for Global Clock g6
14. Device Cell Placement Summary for Global Clock g7
15. Device Cell Placement Summary for Global Clock g8
16. Device Cell Placement Summary for Global Clock g9
17. Device Cell Placement Summary for Global Clock g10
18. Device Cell Placement Summary for Global Clock g11
19. Clock Region Cell Placement per Global Clock: Region X0Y0
20. Clock Region Cell Placement per Global Clock: Region X1Y0
21. Clock Region Cell Placement per Global Clock: Region X0Y1
22. Clock Region Cell Placement per Global Clock: Region X1Y1
23. Clock Region Cell Placement per Global Clock: Region X0Y2
24. Clock Region Cell Placement per Global Clock: Region X1Y2

1. Clock Primitive Utilization
------------------------------

+----------+------+-----------+-----+--------------+--------+
| Type     | Used | Available | LOC | Clock Region | Pblock |
+----------+------+-----------+-----+--------------+--------+
| BUFGCTRL |   12 |        32 |   0 |            0 |      0 |
| BUFH     |    0 |        72 |   0 |            0 |      0 |
| BUFIO    |    0 |        16 |   0 |            0 |      0 |
| BUFMR    |    0 |         8 |   0 |            0 |      0 |
| BUFR     |    0 |        16 |   0 |            0 |      0 |
| MMCM     |    2 |         4 |   1 |            0 |      0 |
| PLL      |    1 |         4 |   1 |            0 |      0 |
+----------+------+-----------+-----+--------------+--------+


2. Global Clock Resources
-------------------------

+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+----------------+--------------------------------+------------------------+
| Global Id | Source Id | Driver Type/Pin | Constraint | Site           | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock          | Driver Pin                     | Net                    |
+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+----------------+--------------------------------+------------------------+
| g0        | src0      | BUFG/O          | None       | BUFGCTRL_X0Y16 | n/a          |                 3 |        4698 |               0 |       24.000 | pll_word_clk   | lvds_pll_inst/BUFG_word_inst/O | lvds_pll_inst/word_clk |
| g1        | src1      | BUFG/O          | None       | BUFGCTRL_X0Y17 | n/a          |                 6 |        3712 |               0 |       10.000 | clk_100        | ps_fclk_BUFG[0]_inst/O         | ps_fclk_BUFG[0]        |
| g2        | src0      | BUFG/O          | None       | BUFGCTRL_X0Y18 | n/a          |                 4 |        1090 |               0 |        4.000 | pll_lvds_clk_1 | lvds_pll_inst/BUFG_lvds_inst/O | lvds_pll_inst/lvds_clk |
| g3        | src2      | BUFG/O          | None       | BUFGCTRL_X0Y0  | n/a          |                 2 |         810 |               0 |       13.468 | pll_data_clk   | hdmi_pll_inst/BUFG_data_inst/O | hdmi_pll_inst/data_clk |
| g4        | src2      | BUFG/O          | None       | BUFGCTRL_X0Y1  | n/a          |                 5 |         406 |               0 |       13.468 | pll_hdmi_clk   | hdmi_pll_inst/BUFG_hdmi_inst/O | hdmi_pll_inst/hdmi_clk |
| g5        | src3      | BUFG/O          | None       | BUFGCTRL_X0Y19 | n/a          |                 3 |         144 |               0 |        5.000 | pll_axi_clk    | cmv_pll_inst/BUFG_axi_inst/O   | cmv_pll_inst/axi_clk   |
| g6        | src3      | BUFG/O          | None       | BUFGCTRL_X0Y20 | n/a          |                 1 |          77 |               1 |      100.000 | pll_spi_clk    | cmv_pll_inst/BUFG_spi_inst/O   | cmv_pll_inst/spi_clk   |
| g7        | src3      | BUFG/O          | None       | BUFGCTRL_X0Y21 | n/a          |                 3 |          57 |               1 |       48.000 | pll_cmv_clk    | cmv_pll_inst/BUFG_cmv_inst/O   | cmv_pll_inst/cmv_clk   |
| g8        | src2      | BUFG/O          | None       | BUFGCTRL_X0Y2  | n/a          |                 3 |          16 |               0 |        2.694 | pll_tmds_clk   | hdmi_pll_inst/BUFG_tmds_inst/O | hdmi_pll_inst/tmds_clk |
| g9        | src4      | BUFG/O          | None       | BUFGCTRL_X0Y3  | n/a          |                 2 |           3 |               0 |       13.468 | sdi_clk        | bufg_inst/O                    | clk_sdi                |
| g10       | src3      | BUFG/O          | None       | BUFGCTRL_X0Y22 | n/a          |                 2 |           2 |               0 |        5.000 | pll_dly_clk    | cmv_pll_inst/BUFG_dly_inst/O   | cmv_pll_inst/dly_clk   |
| g11       | src3      | BUFG/O          | None       | BUFGCTRL_X0Y23 | n/a          |                 1 |           0 |               1 |        4.000 | pll_lvds_clk   | cmv_pll_inst/BUFG_lvds_inst/O  | cmv_pll_inst/lvds_clk  |
+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+----------------+--------------------------------+------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)


3. Global Clock Source Details
------------------------------

+-----------+-----------+--------------------+-----------------+-----------------+--------------+-------------+-----------------+---------------------+----------------+-----------------------------------+----------------------------+
| Source Id | Global Id | Driver Type/Pin    | Constraint      | Site            | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock   | Driver Pin                        | Net                        |
+-----------+-----------+--------------------+-----------------+-----------------+--------------+-------------+-----------------+---------------------+----------------+-----------------------------------+----------------------------+
| src0      | g2        | PLLE2_ADV/CLKOUT0  | PLLE2_ADV_X1Y2  | PLLE2_ADV_X1Y2  | X1Y2         |           1 |               0 |               4.000 | pll_lvds_clk_1 | lvds_pll_inst/pll_inst/CLKOUT0    | lvds_pll_inst/pll_lvds_clk |
| src0      | g0        | PLLE2_ADV/CLKOUT1  | PLLE2_ADV_X1Y2  | PLLE2_ADV_X1Y2  | X1Y2         |           1 |               0 |              24.000 | pll_word_clk   | lvds_pll_inst/pll_inst/CLKOUT1    | lvds_pll_inst/pll_word_clk |
| src1      | g1        | PS7/FCLKCLK[0]     | None            | PS7_X0Y0        | X0Y2         |           1 |               0 |              10.000 | clk_100        | ps7_stub_inst/PS7_inst/FCLKCLK[0] | ps7_stub_inst/FCLKCLK[0]   |
| src2      | g3        | MMCME2_ADV/CLKOUT2 | None            | MMCME2_ADV_X1Y0 | X1Y0         |           1 |               0 |              13.468 | pll_data_clk   | hdmi_pll_inst/mmcm_inst/CLKOUT2   | hdmi_pll_inst/pll_data_clk |
| src2      | g4        | MMCME2_ADV/CLKOUT1 | None            | MMCME2_ADV_X1Y0 | X1Y0         |           1 |               0 |              13.468 | pll_hdmi_clk   | hdmi_pll_inst/mmcm_inst/CLKOUT1   | hdmi_pll_inst/pll_hdmi_clk |
| src2      | g8        | MMCME2_ADV/CLKOUT0 | None            | MMCME2_ADV_X1Y0 | X1Y0         |           1 |               0 |               2.694 | pll_tmds_clk   | hdmi_pll_inst/mmcm_inst/CLKOUT0   | hdmi_pll_inst/pll_tmds_clk |
| src3      | g5        | MMCME2_ADV/CLKOUT3 | MMCME2_ADV_X1Y1 | MMCME2_ADV_X1Y1 | X1Y1         |           1 |               0 |               5.000 | pll_axi_clk    | cmv_pll_inst/mmcm_inst/CLKOUT3    | cmv_pll_inst/pll_axi_clk   |
| src3      | g7        | MMCME2_ADV/CLKOUT1 | MMCME2_ADV_X1Y1 | MMCME2_ADV_X1Y1 | X1Y1         |           1 |               0 |              48.000 | pll_cmv_clk    | cmv_pll_inst/mmcm_inst/CLKOUT1    | cmv_pll_inst/pll_cmv_clk   |
| src3      | g10       | MMCME2_ADV/CLKOUT4 | MMCME2_ADV_X1Y1 | MMCME2_ADV_X1Y1 | X1Y1         |           1 |               0 |               5.000 | pll_dly_clk    | cmv_pll_inst/mmcm_inst/CLKOUT4    | cmv_pll_inst/pll_dly_clk   |
| src3      | g11       | MMCME2_ADV/CLKOUT0 | MMCME2_ADV_X1Y1 | MMCME2_ADV_X1Y1 | X1Y1         |           1 |               0 |               4.000 | pll_lvds_clk   | cmv_pll_inst/mmcm_inst/CLKOUT0    | cmv_pll_inst/pll_lvds_clk  |
| src3      | g6        | MMCME2_ADV/CLKOUT2 | MMCME2_ADV_X1Y1 | MMCME2_ADV_X1Y1 | X1Y1         |           1 |               0 |             100.000 | pll_spi_clk    | cmv_pll_inst/mmcm_inst/CLKOUT2    | cmv_pll_inst/pll_spi_clk   |
| src4      | g9        | IBUFDS/O           | IOB_X0Y28       | IOB_X0Y28       | X0Y0         |           1 |               0 |              13.468 | sdi_clk        | ibufgds_inst/O                    | sdi_clk                    |
+-----------+-----------+--------------------+-----------------+-----------------+--------------+-------------+-----------------+---------------------+----------------+-----------------------------------+----------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** In Constraint column, symbol '*' indicates multiple constraint types applied to the clock source. Please check for potential conflicts.


4. Local Clock Details
----------------------

+----------+-----------------+------------+---------------------+--------------+-------------+-----------------+--------------+-------------+----------------------------------------------------------+--------------------------------------+
| Local Id | Driver Type/Pin | Constraint | Site/BEL            | Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock       | Driver Pin                                               | Net                                  |
+----------+-----------------+------------+---------------------+--------------+-------------+-----------------+--------------+-------------+----------------------------------------------------------+--------------------------------------||
| 0        | FDCE/Q          | None       | SLICE_X49Y57/AFF    | X0Y1         |          64 |               1 |              |             | GEN_FCNT[0].fcnt_div_inst/GEN_STAGE[9].OTHER.FDCE_inst/Q | GEN_FCNT[0].fcnt_div_inst/fcnt_div_4 - Static -
| 1        | FDCE/Q          | None       | SLICE_X42Y58/AFF    | X0Y1         |          64 |               1 |              |             | GEN_FCNT[1].fcnt_div_inst/GEN_STAGE[9].OTHER.FDCE_inst/Q | GEN_FCNT[1].fcnt_div_inst/fcnt_div_3 - Static -
| 2        | FDCE/Q          | None       | SLICE_X46Y60/AFF    | X0Y1         |          64 |               1 |              |             | GEN_FCNT[2].fcnt_div_inst/GEN_STAGE[9].OTHER.FDCE_inst/Q | GEN_FCNT[2].fcnt_div_inst/fcnt_div_2 - Static -
| 3        | FDCE/Q          | None       | SLICE_X35Y53/AFF    | X0Y1         |          64 |               1 |              |             | GEN_FCNT[3].fcnt_div_inst/GEN_STAGE[9].OTHER.FDCE_inst/Q | GEN_FCNT[3].fcnt_div_inst/fcnt_div_1 - Static -
| 4        | FDCE/Q          | None       | SLICE_X37Y49/AFF    | X0Y0         |          64 |               1 |              |             | GEN_FCNT[4].fcnt_div_inst/GEN_STAGE[9].OTHER.FDCE_inst/Q | GEN_FCNT[4].fcnt_div_inst/fcnt_div_0 - Static -
| 5        | FDCE/Q          | None       | SLICE_X47Y60/AFF    | X0Y1         |           1 |               1 |              |             | GEN_FCNT[0].fcnt_div_inst/GEN_STAGE[0].INPUT.FDCE_inst/Q | GEN_FCNT[0].fcnt_div_inst/stage_0    - Static -
| 6        | FDCE/Q          | None       | SLICE_X49Y60/AFF    | X0Y1         |           1 |               1 |              |             | GEN_FCNT[0].fcnt_div_inst/GEN_STAGE[1].OTHER.FDCE_inst/Q | GEN_FCNT[0].fcnt_div_inst/stage_1    - Static -
| 7        | FDCE/Q          | None       | SLICE_X50Y60/AFF    | X1Y1         |           1 |               1 |              |             | GEN_FCNT[0].fcnt_div_inst/GEN_STAGE[2].OTHER.FDCE_inst/Q | GEN_FCNT[0].fcnt_div_inst/stage_2    - Static -
| 8        | FDCE/Q          | None       | SLICE_X50Y59/AFF    | X1Y1         |           1 |               1 |              |             | GEN_FCNT[0].fcnt_div_inst/GEN_STAGE[3].OTHER.FDCE_inst/Q | GEN_FCNT[0].fcnt_div_inst/stage_3    - Static -
| 9        | FDCE/Q          | None       | SLICE_X50Y58/AFF    | X1Y1         |           1 |               1 |              |             | GEN_FCNT[0].fcnt_div_inst/GEN_STAGE[4].OTHER.FDCE_inst/Q | GEN_FCNT[0].fcnt_div_inst/stage_4    - Static -
| 10       | FDCE/Q          | None       | SLICE_X51Y58/AFF    | X1Y1         |           1 |               1 |              |             | GEN_FCNT[0].fcnt_div_inst/GEN_STAGE[5].OTHER.FDCE_inst/Q | GEN_FCNT[0].fcnt_div_inst/stage_5    - Static -
| 11       | FDCE/Q          | None       | SLICE_X51Y57/AFF    | X1Y1         |           1 |               1 |              |             | GEN_FCNT[0].fcnt_div_inst/GEN_STAGE[6].OTHER.FDCE_inst/Q | GEN_FCNT[0].fcnt_div_inst/stage_6    - Static -
| 12       | FDCE/Q          | None       | SLICE_X52Y57/AFF    | X1Y1         |           1 |               1 |              |             | GEN_FCNT[0].fcnt_div_inst/GEN_STAGE[7].OTHER.FDCE_inst/Q | GEN_FCNT[0].fcnt_div_inst/stage_7    - Static -
| 13       | FDCE/Q          | None       | SLICE_X50Y57/AFF    | X1Y1         |           1 |               1 |              |             | GEN_FCNT[0].fcnt_div_inst/GEN_STAGE[8].OTHER.FDCE_inst/Q | GEN_FCNT[0].fcnt_div_inst/stage_8    - Static -
| 14       | FDCE/Q          | None       | SLICE_X36Y62/AFF    | X0Y1         |           1 |               1 |              |             | GEN_FCNT[1].fcnt_div_inst/GEN_STAGE[0].INPUT.FDCE_inst/Q | GEN_FCNT[1].fcnt_div_inst/stage_0    - Static -
| 15       | FDCE/Q          | None       | SLICE_X40Y62/AFF    | X0Y1         |           1 |               1 |              |             | GEN_FCNT[1].fcnt_div_inst/GEN_STAGE[1].OTHER.FDCE_inst/Q | GEN_FCNT[1].fcnt_div_inst/stage_1    - Static -
| 16       | FDCE/Q          | None       | SLICE_X42Y62/AFF    | X0Y1         |           1 |               1 |              |             | GEN_FCNT[1].fcnt_div_inst/GEN_STAGE[2].OTHER.FDCE_inst/Q | GEN_FCNT[1].fcnt_div_inst/stage_2    - Static -
| 17       | FDCE/Q          | None       | SLICE_X41Y61/AFF    | X0Y1         |           1 |               1 |              |             | GEN_FCNT[1].fcnt_div_inst/GEN_STAGE[3].OTHER.FDCE_inst/Q | GEN_FCNT[1].fcnt_div_inst/stage_3    - Static -
| 18       | FDCE/Q          | None       | SLICE_X40Y61/AFF    | X0Y1         |           1 |               1 |              |             | GEN_FCNT[1].fcnt_div_inst/GEN_STAGE[4].OTHER.FDCE_inst/Q | GEN_FCNT[1].fcnt_div_inst/stage_4    - Static -
| 19       | FDCE/Q          | None       | SLICE_X39Y61/AFF    | X0Y1         |           1 |               1 |              |             | GEN_FCNT[1].fcnt_div_inst/GEN_STAGE[5].OTHER.FDCE_inst/Q | GEN_FCNT[1].fcnt_div_inst/stage_5    - Static -
| 20       | FDCE/Q          | None       | SLICE_X39Y60/AFF    | X0Y1         |           1 |               1 |              |             | GEN_FCNT[1].fcnt_div_inst/GEN_STAGE[6].OTHER.FDCE_inst/Q | GEN_FCNT[1].fcnt_div_inst/stage_6    - Static -
| 21       | FDCE/Q          | None       | SLICE_X39Y59/AFF    | X0Y1         |           1 |               1 |              |             | GEN_FCNT[1].fcnt_div_inst/GEN_STAGE[7].OTHER.FDCE_inst/Q | GEN_FCNT[1].fcnt_div_inst/stage_7    - Static -
| 22       | FDCE/Q          | None       | SLICE_X39Y58/AFF    | X0Y1         |           1 |               1 |              |             | GEN_FCNT[1].fcnt_div_inst/GEN_STAGE[8].OTHER.FDCE_inst/Q | GEN_FCNT[1].fcnt_div_inst/stage_8    - Static -
| 23       | FDCE/Q          | None       | SLICE_X49Y64/AFF    | X0Y1         |           1 |               1 |              |             | GEN_FCNT[2].fcnt_div_inst/GEN_STAGE[0].INPUT.FDCE_inst/Q | GEN_FCNT[2].fcnt_div_inst/stage_0    - Static -
| 24       | FDCE/Q          | None       | SLICE_X48Y64/AFF    | X0Y1         |           1 |               1 |              |             | GEN_FCNT[2].fcnt_div_inst/GEN_STAGE[1].OTHER.FDCE_inst/Q | GEN_FCNT[2].fcnt_div_inst/stage_1    - Static -
| 25       | FDCE/Q          | None       | SLICE_X48Y63/AFF    | X0Y1         |           1 |               1 |              |             | GEN_FCNT[2].fcnt_div_inst/GEN_STAGE[2].OTHER.FDCE_inst/Q | GEN_FCNT[2].fcnt_div_inst/stage_2    - Static -
| 26       | FDCE/Q          | None       | SLICE_X49Y63/AFF    | X0Y1         |           1 |               1 |              |             | GEN_FCNT[2].fcnt_div_inst/GEN_STAGE[3].OTHER.FDCE_inst/Q | GEN_FCNT[2].fcnt_div_inst/stage_3    - Static -
| 27       | FDCE/Q          | None       | SLICE_X48Y62/AFF    | X0Y1         |           1 |               1 |              |             | GEN_FCNT[2].fcnt_div_inst/GEN_STAGE[4].OTHER.FDCE_inst/Q | GEN_FCNT[2].fcnt_div_inst/stage_4    - Static -
| 28       | FDCE/Q          | None       | SLICE_X47Y62/AFF    | X0Y1         |           1 |               1 |              |             | GEN_FCNT[2].fcnt_div_inst/GEN_STAGE[5].OTHER.FDCE_inst/Q | GEN_FCNT[2].fcnt_div_inst/stage_5    - Static -
| 29       | FDCE/Q          | None       | SLICE_X48Y61/AFF    | X0Y1         |           1 |               1 |              |             | GEN_FCNT[2].fcnt_div_inst/GEN_STAGE[6].OTHER.FDCE_inst/Q | GEN_FCNT[2].fcnt_div_inst/stage_6    - Static -
| 30       | FDCE/Q          | None       | SLICE_X47Y61/AFF    | X0Y1         |           1 |               1 |              |             | GEN_FCNT[2].fcnt_div_inst/GEN_STAGE[7].OTHER.FDCE_inst/Q | GEN_FCNT[2].fcnt_div_inst/stage_7    - Static -
| 31       | FDCE/Q          | None       | SLICE_X46Y61/AFF    | X0Y1         |           1 |               1 |              |             | GEN_FCNT[2].fcnt_div_inst/GEN_STAGE[8].OTHER.FDCE_inst/Q | GEN_FCNT[2].fcnt_div_inst/stage_8    - Static -
| 32       | FDCE/Q          | None       | SLICE_X31Y55/AFF    | X0Y1         |           1 |               1 |              |             | GEN_FCNT[3].fcnt_div_inst/GEN_STAGE[0].INPUT.FDCE_inst/Q | GEN_FCNT[3].fcnt_div_inst/stage_0    - Static -
| 33       | FDCE/Q          | None       | SLICE_X30Y55/AFF    | X0Y1         |           1 |               1 |              |             | GEN_FCNT[3].fcnt_div_inst/GEN_STAGE[1].OTHER.FDCE_inst/Q | GEN_FCNT[3].fcnt_div_inst/stage_1    - Static -
| 34       | FDCE/Q          | None       | SLICE_X30Y54/AFF    | X0Y1         |           1 |               1 |              |             | GEN_FCNT[3].fcnt_div_inst/GEN_STAGE[2].OTHER.FDCE_inst/Q | GEN_FCNT[3].fcnt_div_inst/stage_2    - Static -
| 35       | FDCE/Q          | None       | SLICE_X30Y53/AFF    | X0Y1         |           1 |               1 |              |             | GEN_FCNT[3].fcnt_div_inst/GEN_STAGE[3].OTHER.FDCE_inst/Q | GEN_FCNT[3].fcnt_div_inst/stage_3    - Static -
| 36       | FDCE/Q          | None       | SLICE_X30Y52/AFF    | X0Y1         |           1 |               1 |              |             | GEN_FCNT[3].fcnt_div_inst/GEN_STAGE[4].OTHER.FDCE_inst/Q | GEN_FCNT[3].fcnt_div_inst/stage_4    - Static -
| 37       | FDCE/Q          | None       | SLICE_X31Y53/AFF    | X0Y1         |           1 |               1 |              |             | GEN_FCNT[3].fcnt_div_inst/GEN_STAGE[5].OTHER.FDCE_inst/Q | GEN_FCNT[3].fcnt_div_inst/stage_5    - Static -
| 38       | FDCE/Q          | None       | SLICE_X32Y53/AFF    | X0Y1         |           1 |               1 |              |             | GEN_FCNT[3].fcnt_div_inst/GEN_STAGE[6].OTHER.FDCE_inst/Q | GEN_FCNT[3].fcnt_div_inst/stage_6    - Static -
| 39       | FDCE/Q          | None       | SLICE_X33Y53/AFF    | X0Y1         |           1 |               1 |              |             | GEN_FCNT[3].fcnt_div_inst/GEN_STAGE[7].OTHER.FDCE_inst/Q | GEN_FCNT[3].fcnt_div_inst/stage_7    - Static -
| 40       | FDCE/Q          | None       | SLICE_X34Y53/AFF    | X0Y1         |           1 |               1 |              |             | GEN_FCNT[3].fcnt_div_inst/GEN_STAGE[8].OTHER.FDCE_inst/Q | GEN_FCNT[3].fcnt_div_inst/stage_8    - Static -
| 41       | FDCE/Q          | None       | SLICE_X29Y51/AFF    | X0Y1         |           1 |               1 |              |             | GEN_FCNT[4].fcnt_div_inst/GEN_STAGE[0].INPUT.FDCE_inst/Q | GEN_FCNT[4].fcnt_div_inst/stage_0    - Static -
| 42       | FDCE/Q          | None       | SLICE_X30Y51/AFF    | X0Y1         |           1 |               1 |              |             | GEN_FCNT[4].fcnt_div_inst/GEN_STAGE[1].OTHER.FDCE_inst/Q | GEN_FCNT[4].fcnt_div_inst/stage_1    - Static -
| 43       | FDCE/Q          | None       | SLICE_X31Y51/AFF    | X0Y1         |           1 |               1 |              |             | GEN_FCNT[4].fcnt_div_inst/GEN_STAGE[2].OTHER.FDCE_inst/Q | GEN_FCNT[4].fcnt_div_inst/stage_2    - Static -
| 44       | FDCE/Q          | None       | SLICE_X32Y51/AFF    | X0Y1         |           1 |               1 |              |             | GEN_FCNT[4].fcnt_div_inst/GEN_STAGE[3].OTHER.FDCE_inst/Q | GEN_FCNT[4].fcnt_div_inst/stage_3    - Static -
| 45       | FDCE/Q          | None       | SLICE_X33Y51/AFF    | X0Y1         |           1 |               1 |              |             | GEN_FCNT[4].fcnt_div_inst/GEN_STAGE[4].OTHER.FDCE_inst/Q | GEN_FCNT[4].fcnt_div_inst/stage_4    - Static -
| 46       | FDCE/Q          | None       | SLICE_X33Y50/AFF    | X0Y1         |           1 |               1 |              |             | GEN_FCNT[4].fcnt_div_inst/GEN_STAGE[5].OTHER.FDCE_inst/Q | GEN_FCNT[4].fcnt_div_inst/stage_5    - Static -
| 47       | FDCE/Q          | None       | SLICE_X33Y49/AFF    | X0Y0         |           1 |               1 |              |             | GEN_FCNT[4].fcnt_div_inst/GEN_STAGE[6].OTHER.FDCE_inst/Q | GEN_FCNT[4].fcnt_div_inst/stage_6    - Static -
| 48       | FDCE/Q          | None       | SLICE_X34Y49/AFF    | X0Y0         |           1 |               1 |              |             | GEN_FCNT[4].fcnt_div_inst/GEN_STAGE[7].OTHER.FDCE_inst/Q | GEN_FCNT[4].fcnt_div_inst/stage_7    - Static -
| 49       | FDCE/Q          | None       | SLICE_X35Y49/AFF    | X0Y0         |           1 |               1 |              |             | GEN_FCNT[4].fcnt_div_inst/GEN_STAGE[8].OTHER.FDCE_inst/Q | GEN_FCNT[4].fcnt_div_inst/stage_8    - Static -
| 50       | LUT1/O          | None       | SLICE_X113Y93/B6LUT | X1Y1         |           1 |               0 |        8.000 | lvds_outclk | lvds_pll_inst/pll_inst_i_1/O                             | lvds_pll_inst/cmv_outclk             - Static -
| 51       | PS7/FCLKCLK[1]  | None       | PS7_X0Y0/PS7        | X0Y2         |           1 |               0 |              |             | ps7_stub_inst/PS7_inst/FCLKCLK[1]                        | ps7_stub_inst/FCLKCLK[1]             - Static -
+----------+-----------------+------------+---------------------+--------------+-------------+-----------------+--------------+-------------+----------------------------------------------------------+--------------------------------------||
* Local Clocks in this context represents only clocks driven by non-global buffers
** Clock Loads column represents the clock pin loads (pin count)
*** Non-Clock Loads column represents the non-clock pin loads (pin count)


5. Clock Regions: Key Resource Utilization
------------------------------------------

+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
|                   | Global Clock |     BUFRs    |    BUFMRs    |    BUFIOs    |     MMCM     |      PLL     |      GT      |      PCI     |    ILOGIC    |    OLOGIC    |      FF      |     LUTM     |    RAMB18    |    RAMB36    |    DSP48E2   |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| X0Y0              |    6 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    8 |    50 | 1539 |  2500 |  552 |  1000 |    0 |    60 |    2 |    30 |    8 |    60 |
| X1Y0              |    4 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    1 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 | 2244 |  3200 |  668 |   850 |    0 |    60 |    8 |    30 |   16 |    40 |
| X0Y1              |    7 |    12 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 | 1400 |  1200 |  595 |   400 |    0 |    20 |    1 |    10 |    4 |    20 |
| X1Y1              |    8 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    1 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |   15 |    50 |    4 |    50 | 2287 |  2600 | 1045 |   850 |    0 |    60 |    4 |    30 |    0 |    40 |
| X0Y2              |    4 |    12 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |  404 |  1200 |  237 |   400 |    0 |    20 |    5 |    10 |    0 |    20 |
| X1Y2              |    6 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    1 |     1 |    0 |     0 |    0 |     0 |   18 |    50 |    4 |    50 | 2666 |  2600 | 1205 |   850 |    0 |    60 |   13 |    30 |    0 |    40 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
* Global Clock column represents track count; while other columns represents cell counts


6. Clock Regions : Global Clock Summary
---------------------------------------

All Modules
+----+----+----+
|    | X0 | X1 |
+----+----+----+
| Y2 |  4 |  6 |
| Y1 |  7 |  8 |
| Y0 |  6 |  4 |
+----+----+----+


7. Device Cell Placement Summary for Global Clock g0
----------------------------------------------------

+-----------+-----------------+-------------------+--------------+-------------+----------------+-------------+----------+----------------+----------+------------------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock        | Period (ns) | Waveform (ns)  | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net                    |
+-----------+-----------------+-------------------+--------------+-------------+----------------+-------------+----------+----------------+----------+------------------------+
| g0        | BUFG/O          | n/a               | pll_word_clk |      24.000 | {0.000 12.000} |        4622 |       33 |              0 |        0 | lvds_pll_inst/word_clk |
+-----------+-----------------+-------------------+--------------+-------------+----------------+-------------+----------+----------------+----------+------------------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types


+----+-----+-------+
|    | X0  | X1    |
+----+-----+-------+
| Y2 |   0 |  2290 |
| Y1 |  16 |  2349 |
| Y0 |   0 |     0 |
+----+-----+-------+


8. Device Cell Placement Summary for Global Clock g1
----------------------------------------------------

+-----------+-----------------+-------------------+---------+-------------+---------------+-------------+----------+----------------+----------+-----------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock   | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net             |
+-----------+-----------------+-------------------+---------+-------------+---------------+-------------+----------+----------------+----------+-----------------+
| g1        | BUFG/O          | n/a               | clk_100 |      10.000 | {0.000 5.000} |        3709 |        0 |              2 |        0 | ps_fclk_BUFG[0] |
+-----------+-----------------+-------------------+---------+-------------+---------------+-------------+----------+----------------+----------+-----------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types


+----+-------+-------+
|    | X0    | X1    |
+----+-------+-------+
| Y2 |   231 |   169 |
| Y1 |   682 |    11 |
| Y0 |  1033 |  1585 |
+----+-------+-------+


9. Device Cell Placement Summary for Global Clock g2
----------------------------------------------------

+-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+------------------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock          | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net                    |
+-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+------------------------+
| g2        | BUFG/O          | n/a               | pll_lvds_clk_1 |       4.000 | {0.000 2.000} |        1024 |       33 |              0 |        0 | lvds_pll_inst/lvds_clk |
+-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+------------------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types


+----+------+------+
|    | X0   | X1   |
+----+------+------+
| Y2 |  134 |  479 |
| Y1 |  280 |  164 |
| Y0 |    0 |    0 |
+----+------+------+


10. Device Cell Placement Summary for Global Clock g3
-----------------------------------------------------

+-----------+-----------------+-------------------+--------------+-------------+---------------+-------------+----------+----------------+----------+------------------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock        | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net                    |
+-----------+-----------------+-------------------+--------------+-------------+---------------+-------------+----------+----------------+----------+------------------------+
| g3        | BUFG/O          | n/a               | pll_data_clk |      13.468 | {0.000 6.734} |         810 |        0 |              0 |        0 | hdmi_pll_inst/data_clk |
+-----------+-----------------+-------------------+--------------+-------------+---------------+-------------+----------+----------------+----------+------------------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types


+----+------+------+
|    | X0   | X1   |
+----+------+------+
| Y2 |    0 |    0 |
| Y1 |    0 |    0 |
| Y0 |  280 |  530 |
+----+------+------+


11. Device Cell Placement Summary for Global Clock g4
-----------------------------------------------------

+-----------+-----------------+-------------------+--------------+-------------+---------------+-------------+----------+----------------+----------+------------------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock        | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net                    |
+-----------+-----------------+-------------------+--------------+-------------+---------------+-------------+----------+----------------+----------+------------------------+
| g4        | BUFG/O          | n/a               | pll_hdmi_clk |      13.468 | {0.000 6.734} |         390 |       16 |              0 |        0 | hdmi_pll_inst/hdmi_clk |
+-----------+-----------------+-------------------+--------------+-------------+---------------+-------------+----------+----------------+----------+------------------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types


+----+------+------+
|    | X0   | X1   |
+----+------+------+
| Y2 |    0 |    4 |
| Y1 |    1 |    4 |
| Y0 |  174 |  223 |
+----+------+------+


12. Device Cell Placement Summary for Global Clock g5
-----------------------------------------------------

+-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+----------------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock       | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net                  |
+-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+----------------------+
| g5        | BUFG/O          | n/a               | pll_axi_clk |       5.000 | {0.000 2.500} |         143 |        0 |              0 |        0 | cmv_pll_inst/axi_clk |
+-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+----------------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types


+----+-----+----+
|    | X0  | X1 |
+----+-----+----+
| Y2 |   1 |  0 |
| Y1 |  81 |  0 |
| Y0 |  61 |  0 |
+----+-----+----+


13. Device Cell Placement Summary for Global Clock g6
-----------------------------------------------------

+-----------+-----------------+-------------------+-------------+-------------+----------------+-------------+----------+----------------+----------+----------------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock       | Period (ns) | Waveform (ns)  | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net                  |
+-----------+-----------------+-------------------+-------------+-------------+----------------+-------------+----------+----------------+----------+----------------------+
| g6        | BUFG/O          | n/a               | pll_spi_clk |     100.000 | {0.000 50.000} |          78 |        0 |              0 |        0 | cmv_pll_inst/spi_clk |
+-----------+-----------------+-------------------+-------------+-------------+----------------+-------------+----------+----------------+----------+----------------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types


+----+-----+----+
|    | X0  | X1 |
+----+-----+----+
| Y2 |  78 |  0 |
| Y1 |   0 |  0 |
| Y0 |   0 |  0 |
+----+-----+----+


14. Device Cell Placement Summary for Global Clock g7
-----------------------------------------------------

+-----------+-----------------+-------------------+-------------+-------------+----------------+-------------+----------+----------------+----------+----------------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock       | Period (ns) | Waveform (ns)  | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net                  |
+-----------+-----------------+-------------------+-------------+-------------+----------------+-------------+----------+----------------+----------+----------------------+
| g7        | BUFG/O          | n/a               | pll_cmv_clk |      48.000 | {0.000 24.000} |          57 |        1 |              0 |        0 | cmv_pll_inst/cmv_clk |
+-----------+-----------------+-------------------+-------------+-------------+----------------+-------------+----------+----------------+----------+----------------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types


+----+-----+----+
|    | X0  | X1 |
+----+-----+----+
| Y2 |   0 |  0 |
| Y1 |  55 |  1 |
| Y0 |   2 |  0 |
+----+-----+----+


15. Device Cell Placement Summary for Global Clock g8
-----------------------------------------------------

+-----------+-----------------+-------------------+--------------+-------------+---------------+-------------+----------+----------------+----------+------------------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock        | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net                    |
+-----------+-----------------+-------------------+--------------+-------------+---------------+-------------+----------+----------------+----------+------------------------+
| g8        | BUFG/O          | n/a               | pll_tmds_clk |       2.694 | {0.000 1.347} |           0 |       16 |              0 |        0 | hdmi_pll_inst/tmds_clk |
+-----------+-----------------+-------------------+--------------+-------------+---------------+-------------+----------+----------------+----------+------------------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types


+----+----+----+
|    | X0 | X1 |
+----+----+----+
| Y2 |  0 |  4 |
| Y1 |  0 |  4 |
| Y0 |  8 |  0 |
+----+----+----+


16. Device Cell Placement Summary for Global Clock g9
-----------------------------------------------------

+-----------+-----------------+-------------------+---------+-------------+---------------+-------------+----------+----------------+----------+---------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock   | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net     |
+-----------+-----------------+-------------------+---------+-------------+---------------+-------------+----------+----------------+----------+---------+
| g9        | BUFG/O          | n/a               | sdi_clk |      13.468 | {0.000 6.734} |           1 |        0 |              1 |        0 | clk_sdi |
+-----------+-----------------+-------------------+---------+-------------+---------------+-------------+----------+----------------+----------+---------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types


+----+----+----+
|    | X0 | X1 |
+----+----+----+
| Y2 |  0 |  0 |
| Y1 |  1 |  0 |
| Y0 |  0 |  1 |
+----+----+----+


17. Device Cell Placement Summary for Global Clock g10
------------------------------------------------------

+-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+----------------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock       | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net                  |
+-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+----------------------+
| g10       | BUFG/O          | n/a               | pll_dly_clk |       5.000 | {0.000 2.500} |           2 |        0 |              0 |        0 | cmv_pll_inst/dly_clk |
+-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+----------------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types


+----+----+----+
|    | X0 | X1 |
+----+----+----+
| Y2 |  0 |  1 |
| Y1 |  0 |  1 |
| Y0 |  0 |  0 |
+----+----+----+


18. Device Cell Placement Summary for Global Clock g11
------------------------------------------------------

+-----------+-----------------+-------------------+--------------+-------------+---------------+-------------+----------+----------------+----------+-----------------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock        | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net                   |
+-----------+-----------------+-------------------+--------------+-------------+---------------+-------------+----------+----------------+----------+-----------------------+
| g11       | BUFG/O          | n/a               | pll_lvds_clk |       4.000 | {0.000 2.000} |           0 |        1 |              0 |        0 | cmv_pll_inst/lvds_clk |
+-----------+-----------------+-------------------+--------------+-------------+---------------+-------------+----------+----------------+----------+-----------------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types


+----+----+----+
|    | X0 | X1 |
+----+----+----+
| Y2 |  0 |  0 |
| Y1 |  0 |  1 |
| Y0 |  0 |  0 |
+----+----+----+


19. Clock Region Cell Placement per Global Clock: Region X0Y0
-------------------------------------------------------------

+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF   | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net                    |
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------+
| g1        | n/a   | BUFG/O          | None       |        1033 |               0 | 1032 |      0 |    1 |   0 |  0 |    0 |   0 |       0 | ps_fclk_BUFG[0]        |
| g3        | n/a   | BUFG/O          | None       |         280 |               0 |  269 |      2 |    2 |   7 |  0 |    0 |   0 |       0 | hdmi_pll_inst/data_clk |
| g4        | n/a   | BUFG/O          | None       |         174 |               0 |  166 |      0 |    0 |   0 |  0 |    0 |   0 |       0 | hdmi_pll_inst/hdmi_clk |
| g5        | n/a   | BUFG/O          | None       |          61 |               0 |   57 |      2 |    1 |   1 |  0 |    0 |   0 |       0 | cmv_pll_inst/axi_clk   |
| g7        | n/a   | BUFG/O          | None       |           2 |               0 |    2 |      0 |    0 |   0 |  0 |    0 |   0 |       0 | cmv_pll_inst/cmv_clk   |
| g8        | n/a   | BUFG/O          | None       |           8 |               0 |    0 |      0 |    0 |   0 |  0 |    0 |   0 |       0 | hdmi_pll_inst/tmds_clk |
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts


20. Clock Region Cell Placement per Global Clock: Region X1Y0
-------------------------------------------------------------

+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF   | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net                    |
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------+
| g1        | n/a   | BUFG/O          | None       |        1585 |               0 | 1576 |      0 |    8 |   0 |  0 |    1 |   0 |       0 | ps_fclk_BUFG[0]        |
| g3        | n/a   | BUFG/O          | None       |         530 |               0 |  445 |     61 |    8 |  16 |  0 |    0 |   0 |       0 | hdmi_pll_inst/data_clk |
| g4        | n/a   | BUFG/O          | None       |         223 |               0 |  223 |      0 |    0 |   0 |  0 |    0 |   0 |       0 | hdmi_pll_inst/hdmi_clk |
| g9        | n/a   | BUFG/O          | None       |           1 |               0 |    0 |      0 |    0 |   0 |  0 |    1 |   0 |       0 | clk_sdi                |
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts


21. Clock Region Cell Placement per Global Clock: Region X0Y1
-------------------------------------------------------------

+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+------------------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF  | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net                    |
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+------------------------+
| g0        | n/a   | BUFG/O          | None       |          16 |               0 |  12 |      4 |    0 |   0 |  0 |    0 |   0 |       0 | lvds_pll_inst/word_clk |
| g1        | n/a   | BUFG/O          | None       |         682 |               0 | 682 |      0 |    0 |   0 |  0 |    0 |   0 |       0 | ps_fclk_BUFG[0]        |
| g2        | n/a   | BUFG/O          | None       |         280 |               0 | 228 |     48 |    1 |   3 |  0 |    0 |   0 |       0 | lvds_pll_inst/lvds_clk |
| g4        | n/a   | BUFG/O          | None       |           1 |               0 |   1 |      0 |    0 |   0 |  0 |    0 |   0 |       0 | hdmi_pll_inst/hdmi_clk |
| g5        | n/a   | BUFG/O          | None       |          81 |               0 |  76 |      3 |    1 |   1 |  0 |    0 |   0 |       0 | cmv_pll_inst/axi_clk   |
| g7        | n/a   | BUFG/O          | None       |          55 |               0 |  54 |      1 |    0 |   0 |  0 |    0 |   0 |       0 | cmv_pll_inst/cmv_clk   |
| g9        | n/a   | BUFG/O          | None       |           1 |               0 |   1 |      0 |    0 |   0 |  0 |    0 |   0 |       0 | clk_sdi                |
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts


22. Clock Region Cell Placement per Global Clock: Region X1Y1
-------------------------------------------------------------

+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF   | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net                    |
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------+
| g0        | n/a   | BUFG/O          | None       |        2349 |               0 | 2121 |    192 |    4 |   0 |  0 |    0 |   0 |       0 | lvds_pll_inst/word_clk |
| g1        | n/a   | BUFG/O          | None       |          11 |               0 |   10 |      0 |    0 |   0 |  0 |    1 |   0 |       0 | ps_fclk_BUFG[0]        |
| g2        | n/a   | BUFG/O          | None       |         164 |               0 |  149 |      0 |    0 |   0 |  0 |    0 |   0 |       0 | lvds_pll_inst/lvds_clk |
| g4        | n/a   | BUFG/O          | None       |           4 |               0 |    0 |      0 |    0 |   0 |  0 |    0 |   0 |       0 | hdmi_pll_inst/hdmi_clk |
| g7        | n/a   | BUFG/O          | None       |           0 |               1 |    0 |      0 |    0 |   0 |  0 |    0 |   0 |       0 | cmv_pll_inst/cmv_clk   |
| g8        | n/a   | BUFG/O          | None       |           4 |               0 |    0 |      0 |    0 |   0 |  0 |    0 |   0 |       0 | hdmi_pll_inst/tmds_clk |
| g10       | n/a   | BUFG/O          | None       |           1 |               0 |    0 |      0 |    0 |   0 |  0 |    0 |   0 |       0 | cmv_pll_inst/dly_clk   |
| g11       | n/a   | BUFG/O          | None       |           0 |               1 |    0 |      0 |    0 |   0 |  0 |    0 |   0 |       0 | cmv_pll_inst/lvds_clk  |
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts


23. Clock Region Cell Placement per Global Clock: Region X0Y2
-------------------------------------------------------------

+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+------------------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF  | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net                    |
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+------------------------+
| g1        | n/a   | BUFG/O          | None       |         231 |               0 | 225 |      0 |    5 |   0 |  0 |    0 |   0 |       0 | ps_fclk_BUFG[0]        |
| g2        | n/a   | BUFG/O          | None       |         134 |               0 | 103 |     26 |    5 |   0 |  0 |    0 |   0 |       0 | lvds_pll_inst/lvds_clk |
| g5        | n/a   | BUFG/O          | None       |           1 |               0 |   0 |      0 |    0 |   0 |  0 |    0 |   0 |       0 | cmv_pll_inst/axi_clk   |
| g6        | n/a   | BUFG/O          | None       |          77 |               1 |  76 |      1 |    0 |   0 |  0 |    0 |   0 |       0 | cmv_pll_inst/spi_clk   |
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts


24. Clock Region Cell Placement per Global Clock: Region X1Y2
-------------------------------------------------------------

+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF   | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net                    |
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------+
| g0        | n/a   | BUFG/O          | None       |        2290 |               0 | 2054 |    195 |    4 |   0 |  0 |    0 |   0 |       0 | lvds_pll_inst/word_clk |
| g1        | n/a   | BUFG/O          | None       |         169 |               0 |  160 |      0 |    9 |   0 |  0 |    0 |   0 |       0 | ps_fclk_BUFG[0]        |
| g2        | n/a   | BUFG/O          | None       |         479 |               0 |  452 |      0 |    9 |   0 |  0 |    0 |   0 |       0 | lvds_pll_inst/lvds_clk |
| g4        | n/a   | BUFG/O          | None       |           4 |               0 |    0 |      0 |    0 |   0 |  0 |    0 |   0 |       0 | hdmi_pll_inst/hdmi_clk |
| g8        | n/a   | BUFG/O          | None       |           4 |               0 |    0 |      0 |    0 |   0 |  0 |    0 |   0 |       0 | hdmi_pll_inst/tmds_clk |
| g10       | n/a   | BUFG/O          | None       |           1 |               0 |    0 |      0 |    0 |   0 |  0 |    0 |   0 |       0 | cmv_pll_inst/dly_clk   |
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts



# Location of BUFG Primitives 
set_property LOC BUFGCTRL_X0Y17 [get_cells ps_fclk_BUFG[0]_inst]
set_property LOC BUFGCTRL_X0Y16 [get_cells lvds_pll_inst/BUFG_word_inst]
set_property LOC BUFGCTRL_X0Y18 [get_cells lvds_pll_inst/BUFG_lvds_inst]
set_property LOC BUFGCTRL_X0Y2 [get_cells hdmi_pll_inst/BUFG_tmds_inst]
set_property LOC BUFGCTRL_X0Y1 [get_cells hdmi_pll_inst/BUFG_hdmi_inst]
set_property LOC BUFGCTRL_X0Y0 [get_cells hdmi_pll_inst/BUFG_data_inst]
set_property LOC BUFGCTRL_X0Y20 [get_cells cmv_pll_inst/BUFG_spi_inst]
set_property LOC BUFGCTRL_X0Y23 [get_cells cmv_pll_inst/BUFG_lvds_inst]
set_property LOC BUFGCTRL_X0Y22 [get_cells cmv_pll_inst/BUFG_dly_inst]
set_property LOC BUFGCTRL_X0Y21 [get_cells cmv_pll_inst/BUFG_cmv_inst]
set_property LOC BUFGCTRL_X0Y19 [get_cells cmv_pll_inst/BUFG_axi_inst]
set_property LOC BUFGCTRL_X0Y3 [get_cells bufg_inst]

# Location of IO Primitives which is load of clock spine
set_property LOC IOB_X1Y93 [get_cells cmv_clk_OBUF_inst]
set_property LOC IOB_X1Y54 [get_cells OBUFDS_inst]

# Location of clock ports
set_property LOC IOB_X0Y27 [get_ports sdi_clk_n]
set_property LOC IOB_X0Y28 [get_ports sdi_clk_p]

# Clock net "ps_fclk_BUFG[0]" driven by instance "ps_fclk_BUFG[0]_inst" located at site "BUFGCTRL_X0Y17"
#startgroup
create_pblock {CLKAG_ps_fclk_BUFG[0]}
add_cells_to_pblock [get_pblocks  {CLKAG_ps_fclk_BUFG[0]}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL && NAME!=hdmi_pll_inst/mmcm_inst && NAME!=cmv_pll_inst/mmcm_inst} -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ps_fclk_BUFG[0]"}]]]
resize_pblock [get_pblocks {CLKAG_ps_fclk_BUFG[0]}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
#endgroup

# Clock net "lvds_pll_inst/word_clk" driven by instance "lvds_pll_inst/BUFG_word_inst" located at site "BUFGCTRL_X0Y16"
#startgroup
create_pblock {CLKAG_lvds_pll_inst/word_clk}
add_cells_to_pblock [get_pblocks  {CLKAG_lvds_pll_inst/word_clk}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="lvds_pll_inst/word_clk"}]]]
resize_pblock [get_pblocks {CLKAG_lvds_pll_inst/word_clk}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
#endgroup

# Clock net "lvds_pll_inst/lvds_clk" driven by instance "lvds_pll_inst/BUFG_lvds_inst" located at site "BUFGCTRL_X0Y18"
#startgroup
create_pblock {CLKAG_lvds_pll_inst/lvds_clk}
add_cells_to_pblock [get_pblocks  {CLKAG_lvds_pll_inst/lvds_clk}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="lvds_pll_inst/lvds_clk"}]]]
resize_pblock [get_pblocks {CLKAG_lvds_pll_inst/lvds_clk}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
#endgroup

# Clock net "hdmi_pll_inst/tmds_clk" driven by instance "hdmi_pll_inst/BUFG_tmds_inst" located at site "BUFGCTRL_X0Y2"
#startgroup
create_pblock {CLKAG_hdmi_pll_inst/tmds_clk}
add_cells_to_pblock [get_pblocks  {CLKAG_hdmi_pll_inst/tmds_clk}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="hdmi_pll_inst/tmds_clk"}]]]
resize_pblock [get_pblocks {CLKAG_hdmi_pll_inst/tmds_clk}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
#endgroup

# Clock net "hdmi_pll_inst/hdmi_clk" driven by instance "hdmi_pll_inst/BUFG_hdmi_inst" located at site "BUFGCTRL_X0Y1"
#startgroup
create_pblock {CLKAG_hdmi_pll_inst/hdmi_clk}
add_cells_to_pblock [get_pblocks  {CLKAG_hdmi_pll_inst/hdmi_clk}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="hdmi_pll_inst/hdmi_clk"}]]]
resize_pblock [get_pblocks {CLKAG_hdmi_pll_inst/hdmi_clk}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
#endgroup

# Clock net "hdmi_pll_inst/data_clk" driven by instance "hdmi_pll_inst/BUFG_data_inst" located at site "BUFGCTRL_X0Y0"
#startgroup
create_pblock {CLKAG_hdmi_pll_inst/data_clk}
add_cells_to_pblock [get_pblocks  {CLKAG_hdmi_pll_inst/data_clk}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="hdmi_pll_inst/data_clk"}]]]
resize_pblock [get_pblocks {CLKAG_hdmi_pll_inst/data_clk}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
#endgroup

# Clock net "cmv_pll_inst/spi_clk" driven by instance "cmv_pll_inst/BUFG_spi_inst" located at site "BUFGCTRL_X0Y20"
#startgroup
create_pblock {CLKAG_cmv_pll_inst/spi_clk}
add_cells_to_pblock [get_pblocks  {CLKAG_cmv_pll_inst/spi_clk}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="cmv_pll_inst/spi_clk"}]]]
resize_pblock [get_pblocks {CLKAG_cmv_pll_inst/spi_clk}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
#endgroup

# Clock net "cmv_pll_inst/dly_clk" driven by instance "cmv_pll_inst/BUFG_dly_inst" located at site "BUFGCTRL_X0Y22"
#startgroup
create_pblock {CLKAG_cmv_pll_inst/dly_clk}
add_cells_to_pblock [get_pblocks  {CLKAG_cmv_pll_inst/dly_clk}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="cmv_pll_inst/dly_clk"}]]]
resize_pblock [get_pblocks {CLKAG_cmv_pll_inst/dly_clk}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
#endgroup

# Clock net "cmv_pll_inst/cmv_clk" driven by instance "cmv_pll_inst/BUFG_cmv_inst" located at site "BUFGCTRL_X0Y21"
#startgroup
create_pblock {CLKAG_cmv_pll_inst/cmv_clk}
add_cells_to_pblock [get_pblocks  {CLKAG_cmv_pll_inst/cmv_clk}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL && NAME!=cmv_clk_OBUF_inst} -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="cmv_pll_inst/cmv_clk"}]]]
resize_pblock [get_pblocks {CLKAG_cmv_pll_inst/cmv_clk}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
#endgroup

# Clock net "cmv_pll_inst/axi_clk" driven by instance "cmv_pll_inst/BUFG_axi_inst" located at site "BUFGCTRL_X0Y19"
#startgroup
create_pblock {CLKAG_cmv_pll_inst/axi_clk}
add_cells_to_pblock [get_pblocks  {CLKAG_cmv_pll_inst/axi_clk}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="cmv_pll_inst/axi_clk"}]]]
resize_pblock [get_pblocks {CLKAG_cmv_pll_inst/axi_clk}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
#endgroup

# Clock net "clk_sdi" driven by instance "bufg_inst" located at site "BUFGCTRL_X0Y3"
#startgroup
create_pblock {CLKAG_clk_sdi}
add_cells_to_pblock [get_pblocks  {CLKAG_clk_sdi}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL && NAME!=hdmi_pll_inst/mmcm_inst} -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_sdi"}]]]
resize_pblock [get_pblocks {CLKAG_clk_sdi}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
#endgroup
