---------------------------------------------------------------------------- -- hdmi_pll.vhd -- Axiom Alpha HDMI related PLLs (Reconf) -- Version 1.2 -- -- Copyright (C) 2013-2024 H.Poetzl -- -- This program is free software: you can redistribute it and/or -- modify it under the terms of the GNU General Public License -- as published by the Free Software Foundation, either version -- 2 of the License, or (at your option) any later version. -- ---------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.ALL; use IEEE.numeric_std.ALL; package hdmi_pll_pkg is type hdmi_config is ( HDMI_5940KHZ, HDMI_6400KHZ, HDMI_6600KHZ, HDMI_6750KHZ, HDMI_6875KHZ, HDMI_7425KHZ, HDMI_7500KHZ, HDMI_8000KHZ, HDMI_8250KHZ, HDMI_8640KHZ, HDMI_9000KHZ, HDMI_9600KHZ, HDMI_9900KHZ, HDMI_10000KHZ, HDMI_10800KHZ, HDMI_11000KHZ, HDMI_12000KHZ, HDMI_12375KHZ, HDMI_12500KHZ, HDMI_13500KHZ, HDMI_13750KHZ, HDMI_14400KHZ, HDMI_14850KHZ, HDMI_15000KHZ, HDMI_16000KHZ, HDMI_16500KHZ, HDMI_18000KHZ, HDMI_20000KHZ, HDMI_20625KHZ, HDMI_21600KHZ, HDMI_24000KHZ, HDMI_24750KHZ, HDMI_25000KHZ, HDMI_27000KHZ, HDMI_27500KHZ, HDMI_29700KHZ, HDMI_30000KHZ, HDMI_32000KHZ, HDMI_33000KHZ, HDMI_36000KHZ, HDMI_37125KHZ, HDMI_40000KHZ, HDMI_41250KHZ, HDMI_43200KHZ, HDMI_48000KHZ, HDMI_49500KHZ, HDMI_50000KHZ, HDMI_54000KHZ, HDMI_55000KHZ, HDMI_60000KHZ, HDMI_72000KHZ, HDMI_74250KHZ, HDMI_80000KHZ, HDMI_82500KHZ, HDMI_100000KHZ, HDMI_108000KHZ, HDMI_120000KHZ, HDMI_148500KHZ, HDMI_160000KHZ, HDMI_165000KHZ ); end; library IEEE; use IEEE.std_logic_1164.ALL; use IEEE.numeric_std.ALL; library unisim; use unisim.VCOMPONENTS.ALL; use work.axi3ml_pkg.ALL; -- AXI3 Lite Master use work.vivado_pkg.ALL; -- Vivado Attributes use work.hdmi_pll_pkg.ALL; entity hdmi_pll is generic ( PLL_CONFIG : hdmi_config := HDMI_165000KHZ ); port ( ref_clk_in : in std_logic; -- input clock to FPGA -- pll_reset : in std_logic; -- PLL reset pll_pwrdwn : in std_logic; -- PLL power down pll_locked : out std_logic; -- PLL locked -- tmds_clk : out std_logic; -- TMDS bit clock hdmi_clk : out std_logic; -- HDMI output clock data_clk : out std_logic; -- HDMI data clock -- s_axi_aclk : in std_logic; s_axi_areset_n : in std_logic; -- s_axi_ro : out axi3ml_read_in_r; s_axi_ri : in axi3ml_read_out_r; s_axi_wo : out axi3ml_write_in_r; s_axi_wi : in axi3ml_write_out_r ); end entity hdmi_pll; architecture RTL of hdmi_pll is type hdmi_config_r is record CLKIN1_PERIOD : real; CLKFBOUT_MULT_F : real; DIVCLK_DIVIDE : natural; -- CLKOUT0_DIVIDE_F : real; CLKOUT1_DIVIDE : natural; CLKOUT2_DIVIDE : natural; end record; type hdmi_config_a is array (hdmi_config) of hdmi_config_r; constant conf_c : hdmi_config_a := ( HDMI_5940KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 37.125, DIVCLK_DIVIDE => 5, -- CLKOUT0_DIVIDE_F => 25.0, CLKOUT1_DIVIDE => 125, CLKOUT2_DIVIDE => 125 ), HDMI_6400KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 8.000, DIVCLK_DIVIDE => 1, -- CLKOUT0_DIVIDE_F => 25.0, CLKOUT1_DIVIDE => 125, CLKOUT2_DIVIDE => 125 ), HDMI_6600KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 8.250, DIVCLK_DIVIDE => 1, -- CLKOUT0_DIVIDE_F => 25.0, CLKOUT1_DIVIDE => 125, CLKOUT2_DIVIDE => 125 ), HDMI_6750KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 37.125, DIVCLK_DIVIDE => 5, -- CLKOUT0_DIVIDE_F => 22.0, CLKOUT1_DIVIDE => 110, CLKOUT2_DIVIDE => 110 ), HDMI_6875KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 8.250, DIVCLK_DIVIDE => 1, -- CLKOUT0_DIVIDE_F => 24.0, CLKOUT1_DIVIDE => 120, CLKOUT2_DIVIDE => 120 ), HDMI_7425KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 37.125, DIVCLK_DIVIDE => 5, -- CLKOUT0_DIVIDE_F => 20.0, CLKOUT1_DIVIDE => 100, CLKOUT2_DIVIDE => 100 ), HDMI_7500KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 8.250, DIVCLK_DIVIDE => 1, -- CLKOUT0_DIVIDE_F => 22.0, CLKOUT1_DIVIDE => 110, CLKOUT2_DIVIDE => 110 ), HDMI_8000KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 10.000, DIVCLK_DIVIDE => 1, -- CLKOUT0_DIVIDE_F => 25.0, CLKOUT1_DIVIDE => 125, CLKOUT2_DIVIDE => 125 ), HDMI_8250KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 8.250, DIVCLK_DIVIDE => 1, -- CLKOUT0_DIVIDE_F => 20.0, CLKOUT1_DIVIDE => 100, CLKOUT2_DIVIDE => 100 ), HDMI_8640KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 54.000, DIVCLK_DIVIDE => 5, -- CLKOUT0_DIVIDE_F => 25.0, CLKOUT1_DIVIDE => 125, CLKOUT2_DIVIDE => 125 ), HDMI_9000KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 54.000, DIVCLK_DIVIDE => 5, -- CLKOUT0_DIVIDE_F => 24.0, CLKOUT1_DIVIDE => 120, CLKOUT2_DIVIDE => 120 ), HDMI_9600KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 12.000, DIVCLK_DIVIDE => 1, -- CLKOUT0_DIVIDE_F => 25.0, CLKOUT1_DIVIDE => 125, CLKOUT2_DIVIDE => 125 ), HDMI_9900KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 37.125, DIVCLK_DIVIDE => 5, -- CLKOUT0_DIVIDE_F => 15.0, CLKOUT1_DIVIDE => 75, CLKOUT2_DIVIDE => 75 ), HDMI_10000KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 12.000, DIVCLK_DIVIDE => 1, -- CLKOUT0_DIVIDE_F => 24.0, CLKOUT1_DIVIDE => 120, CLKOUT2_DIVIDE => 120 ), HDMI_10800KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 54.000, DIVCLK_DIVIDE => 5, -- CLKOUT0_DIVIDE_F => 20.0, CLKOUT1_DIVIDE => 100, CLKOUT2_DIVIDE => 100 ), HDMI_11000KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 8.250, DIVCLK_DIVIDE => 1, -- CLKOUT0_DIVIDE_F => 15.0, CLKOUT1_DIVIDE => 75, CLKOUT2_DIVIDE => 75 ), HDMI_12000KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 12.000, DIVCLK_DIVIDE => 1, -- CLKOUT0_DIVIDE_F => 20.0, CLKOUT1_DIVIDE => 100, CLKOUT2_DIVIDE => 100 ), HDMI_12375KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 37.125, DIVCLK_DIVIDE => 5, -- CLKOUT0_DIVIDE_F => 12.0, CLKOUT1_DIVIDE => 60, CLKOUT2_DIVIDE => 60 ), HDMI_12500KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 10.000, DIVCLK_DIVIDE => 1, -- CLKOUT0_DIVIDE_F => 16.0, CLKOUT1_DIVIDE => 80, CLKOUT2_DIVIDE => 80 ), HDMI_13500KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 54.000, DIVCLK_DIVIDE => 5, -- CLKOUT0_DIVIDE_F => 16.0, CLKOUT1_DIVIDE => 80, CLKOUT2_DIVIDE => 80 ), HDMI_13750KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 8.250, DIVCLK_DIVIDE => 1, -- CLKOUT0_DIVIDE_F => 12.0, CLKOUT1_DIVIDE => 60, CLKOUT2_DIVIDE => 60 ), HDMI_14400KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 54.000, DIVCLK_DIVIDE => 5, -- CLKOUT0_DIVIDE_F => 15.0, CLKOUT1_DIVIDE => 75, CLKOUT2_DIVIDE => 75 ), HDMI_14850KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 37.125, DIVCLK_DIVIDE => 5, -- CLKOUT0_DIVIDE_F => 10.0, CLKOUT1_DIVIDE => 50, CLKOUT2_DIVIDE => 50 ), HDMI_15000KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 12.000, DIVCLK_DIVIDE => 1, -- CLKOUT0_DIVIDE_F => 16.0, CLKOUT1_DIVIDE => 80, CLKOUT2_DIVIDE => 80 ), HDMI_16000KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 12.000, DIVCLK_DIVIDE => 1, -- CLKOUT0_DIVIDE_F => 15.0, CLKOUT1_DIVIDE => 75, CLKOUT2_DIVIDE => 75 ), HDMI_16500KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 8.250, DIVCLK_DIVIDE => 1, -- CLKOUT0_DIVIDE_F => 10.0, CLKOUT1_DIVIDE => 50, CLKOUT2_DIVIDE => 50 ), HDMI_18000KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 54.000, DIVCLK_DIVIDE => 5, -- CLKOUT0_DIVIDE_F => 12.0, CLKOUT1_DIVIDE => 60, CLKOUT2_DIVIDE => 60 ), HDMI_20000KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 12.000, DIVCLK_DIVIDE => 1, -- CLKOUT0_DIVIDE_F => 12.0, CLKOUT1_DIVIDE => 60, CLKOUT2_DIVIDE => 60 ), HDMI_20625KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 8.250, DIVCLK_DIVIDE => 1, -- CLKOUT0_DIVIDE_F => 8.0, CLKOUT1_DIVIDE => 40, CLKOUT2_DIVIDE => 40 ), HDMI_21600KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 54.000, DIVCLK_DIVIDE => 5, -- CLKOUT0_DIVIDE_F => 10.0, CLKOUT1_DIVIDE => 50, CLKOUT2_DIVIDE => 50 ), HDMI_24000KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 12.000, DIVCLK_DIVIDE => 1, -- CLKOUT0_DIVIDE_F => 10.0, CLKOUT1_DIVIDE => 50, CLKOUT2_DIVIDE => 50 ), HDMI_24750KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 37.125, DIVCLK_DIVIDE => 5, -- CLKOUT0_DIVIDE_F => 6.0, CLKOUT1_DIVIDE => 30, CLKOUT2_DIVIDE => 30 ), HDMI_25000KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 10.000, DIVCLK_DIVIDE => 1, -- CLKOUT0_DIVIDE_F => 8.0, CLKOUT1_DIVIDE => 40, CLKOUT2_DIVIDE => 40 ), HDMI_27000KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 54.000, DIVCLK_DIVIDE => 5, -- CLKOUT0_DIVIDE_F => 8.0, CLKOUT1_DIVIDE => 40, CLKOUT2_DIVIDE => 40 ), HDMI_27500KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 8.250, DIVCLK_DIVIDE => 1, -- CLKOUT0_DIVIDE_F => 6.0, CLKOUT1_DIVIDE => 30, CLKOUT2_DIVIDE => 30 ), HDMI_29700KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 37.125, DIVCLK_DIVIDE => 5, -- CLKOUT0_DIVIDE_F => 5.0, CLKOUT1_DIVIDE => 25, CLKOUT2_DIVIDE => 25 ), HDMI_30000KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 12.000, DIVCLK_DIVIDE => 1, -- CLKOUT0_DIVIDE_F => 8.0, CLKOUT1_DIVIDE => 40, CLKOUT2_DIVIDE => 40 ), HDMI_32000KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 8.000, DIVCLK_DIVIDE => 1, -- CLKOUT0_DIVIDE_F => 5.0, CLKOUT1_DIVIDE => 25, CLKOUT2_DIVIDE => 25 ), HDMI_33000KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 8.250, DIVCLK_DIVIDE => 1, -- CLKOUT0_DIVIDE_F => 5.0, CLKOUT1_DIVIDE => 25, CLKOUT2_DIVIDE => 25 ), HDMI_36000KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 54.000, DIVCLK_DIVIDE => 5, -- CLKOUT0_DIVIDE_F => 6.0, CLKOUT1_DIVIDE => 30, CLKOUT2_DIVIDE => 30 ), HDMI_37125KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 37.125, DIVCLK_DIVIDE => 5, -- CLKOUT0_DIVIDE_F => 4.0, CLKOUT1_DIVIDE => 20, CLKOUT2_DIVIDE => 20 ), HDMI_40000KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 12.000, DIVCLK_DIVIDE => 1, -- CLKOUT0_DIVIDE_F => 6.0, CLKOUT1_DIVIDE => 30, CLKOUT2_DIVIDE => 30 ), HDMI_41250KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 8.250, DIVCLK_DIVIDE => 1, -- CLKOUT0_DIVIDE_F => 4.0, CLKOUT1_DIVIDE => 20, CLKOUT2_DIVIDE => 20 ), HDMI_43200KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 54.000, DIVCLK_DIVIDE => 5, -- CLKOUT0_DIVIDE_F => 5.0, CLKOUT1_DIVIDE => 25, CLKOUT2_DIVIDE => 25 ), HDMI_48000KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 12.000, DIVCLK_DIVIDE => 1, -- CLKOUT0_DIVIDE_F => 5.0, CLKOUT1_DIVIDE => 25, CLKOUT2_DIVIDE => 25 ), HDMI_49500KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 37.125, DIVCLK_DIVIDE => 5, -- CLKOUT0_DIVIDE_F => 3.0, CLKOUT1_DIVIDE => 15, CLKOUT2_DIVIDE => 15 ), HDMI_50000KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 10.000, DIVCLK_DIVIDE => 1, -- CLKOUT0_DIVIDE_F => 4.0, CLKOUT1_DIVIDE => 20, CLKOUT2_DIVIDE => 20 ), HDMI_54000KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 54.000, DIVCLK_DIVIDE => 5, -- CLKOUT0_DIVIDE_F => 4.0, CLKOUT1_DIVIDE => 20, CLKOUT2_DIVIDE => 20 ), HDMI_55000KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 8.250, DIVCLK_DIVIDE => 1, -- CLKOUT0_DIVIDE_F => 3.0, CLKOUT1_DIVIDE => 15, CLKOUT2_DIVIDE => 15 ), HDMI_60000KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 12.000, DIVCLK_DIVIDE => 1, -- CLKOUT0_DIVIDE_F => 4.0, CLKOUT1_DIVIDE => 20, CLKOUT2_DIVIDE => 20 ), HDMI_72000KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 54.000, DIVCLK_DIVIDE => 5, -- CLKOUT0_DIVIDE_F => 3.0, CLKOUT1_DIVIDE => 15, CLKOUT2_DIVIDE => 15 ), HDMI_74250KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 37.125, DIVCLK_DIVIDE => 5, -- CLKOUT0_DIVIDE_F => 2.0, CLKOUT1_DIVIDE => 10, CLKOUT2_DIVIDE => 10 ), HDMI_80000KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 12.000, DIVCLK_DIVIDE => 1, -- CLKOUT0_DIVIDE_F => 3.0, CLKOUT1_DIVIDE => 15, CLKOUT2_DIVIDE => 15 ), HDMI_82500KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 8.250, DIVCLK_DIVIDE => 1, -- CLKOUT0_DIVIDE_F => 2.0, CLKOUT1_DIVIDE => 10, CLKOUT2_DIVIDE => 10 ), HDMI_100000KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 10.000, DIVCLK_DIVIDE => 1, -- CLKOUT0_DIVIDE_F => 2.0, CLKOUT1_DIVIDE => 10, CLKOUT2_DIVIDE => 10 ), HDMI_108000KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 54.000, DIVCLK_DIVIDE => 5, -- CLKOUT0_DIVIDE_F => 2.0, CLKOUT1_DIVIDE => 10, CLKOUT2_DIVIDE => 10 ), HDMI_120000KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 12.000, DIVCLK_DIVIDE => 1, -- CLKOUT0_DIVIDE_F => 2.0, CLKOUT1_DIVIDE => 10, CLKOUT2_DIVIDE => 10 ), HDMI_148500KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 37.125, DIVCLK_DIVIDE => 5, -- CLKOUT0_DIVIDE_F => 1.0, CLKOUT1_DIVIDE => 5, CLKOUT2_DIVIDE => 5 ), HDMI_160000KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 8.000, DIVCLK_DIVIDE => 1, -- CLKOUT0_DIVIDE_F => 1.0, CLKOUT1_DIVIDE => 5, CLKOUT2_DIVIDE => 5 ), HDMI_165000KHZ => ( CLKIN1_PERIOD => 10.000, CLKFBOUT_MULT_F => 8.250, DIVCLK_DIVIDE => 1, -- CLKOUT0_DIVIDE_F => 1.0, CLKOUT1_DIVIDE => 5, CLKOUT2_DIVIDE => 5 ) ); signal pll_fbout : std_logic; signal pll_fbin : std_logic; signal pll_tmds_clk : std_logic; signal pll_hdmi_clk : std_logic; signal pll_data_clk : std_logic; signal pll_dclk : std_logic; signal pll_den : std_logic; signal pll_dwe : std_logic; signal pll_drdy : std_logic; signal pll_daddr : std_logic_vector(6 downto 0); signal pll_do : std_logic_vector(15 downto 0); signal pll_di : std_logic_vector(15 downto 0); signal pll_psclk : std_logic := '0'; signal pll_psen : std_logic := '0'; signal pll_psincdec : std_logic := '0'; begin mmcm_inst : MMCME2_ADV generic map ( BANDWIDTH => "LOW", CLKIN1_PERIOD => conf_c(PLL_CONFIG).CLKIN1_PERIOD, CLKFBOUT_MULT_F => conf_c(PLL_CONFIG).CLKFBOUT_MULT_F, CLKOUT0_DIVIDE_F => conf_c(PLL_CONFIG).CLKOUT0_DIVIDE_F, CLKOUT1_DIVIDE => conf_c(PLL_CONFIG).CLKOUT1_DIVIDE, CLKOUT2_DIVIDE => conf_c(PLL_CONFIG).CLKOUT2_DIVIDE, -- CLKOUT0_PHASE => 0.0, CLKOUT1_PHASE => 0.0, CLKOUT2_PHASE => 0.0, -- DIVCLK_DIVIDE => conf_c(PLL_CONFIG).DIVCLK_DIVIDE ) port map ( CLKIN1 => ref_clk_in, CLKIN2 => ref_clk_in, CLKINSEL => '1', CLKFBOUT => pll_fbout, CLKFBIN => pll_fbin, CLKOUT0 => pll_tmds_clk, CLKOUT1 => pll_hdmi_clk, CLKOUT2 => pll_data_clk, LOCKED => pll_locked, PWRDWN => pll_pwrdwn, RST => pll_reset, -- DCLK => pll_dclk, DEN => pll_den, DWE => pll_dwe, DRDY => pll_drdy, -- DADDR => pll_daddr, DO => pll_do, DI => pll_di, -- PSCLK => pll_psclk, PSEN => pll_psen, PSINCDEC => pll_psincdec ); pll_fbin <= pll_fbout; reg_pll_inst : entity work.reg_pll port map ( s_axi_aclk => s_axi_aclk, s_axi_areset_n => s_axi_areset_n, -- s_axi_ro => s_axi_ro, s_axi_ri => s_axi_ri, s_axi_wo => s_axi_wo, s_axi_wi => s_axi_wi, -- pll_dclk => pll_dclk, pll_den => pll_den, pll_dwe => pll_dwe, pll_drdy => pll_drdy, -- pll_daddr => pll_daddr, pll_dout => pll_do, pll_din => pll_di ); BUFG_tmds_inst : BUFG port map ( I => pll_tmds_clk, O => tmds_clk ); BUFG_hdmi_inst : BUFG port map ( I => pll_hdmi_clk, O => hdmi_clk ); BUFG_data_inst : BUFG port map ( I => pll_data_clk, O => data_clk ); end RTL;