AXIOM Beta CMV12000 ZIF Sensor Board
Copyright (C) 2015 Herbert Pötzl
Licensed under CERN OHL v1.2
V0.15
R1.4
0
0
VC
EC
FC
<b>Parallella</b> eagle library<br>
<br>
By Sylvain Munaut
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<b>Test Pins/Pads</b><p>
Cream on SMD OFF.<br>
new: Attribute TP_SIGNAL_NAME<br>
<author>Created by librarian@cadsoft.de</author>
<b>TEST PAD</b>
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<li><b>SOT996-2/3</b><hr>
<ul><li>XSON8U: plastic extremely thin small outline package; no leads;8 terminals; UTLP based; body 3 x 2 x 0.5 mm
<li><u>JEDEC</u>:
<li><u>IEC</u>: --
<li><u>JEITA</u>: --</ul>
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<b>EAGLE Design Rules</b>
<p>
Die Standard-Design-Rules sind so gewählt, dass sie für
die meisten Anwendungen passen. Sollte ihre Platine
besondere Anforderungen haben, treffen Sie die erforderlichen
Einstellungen hier und speichern die Design Rules unter
einem neuen Namen ab.
<b>Laen's PCB Order Design Rules</b>
<p>
Please make sure your boards conform to these design rules.
Since Version 6.2.2 text objects can contain more than one line,
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