----------------------------------------------------------------------------
--  slow_i2c.vhd
--	ZedBoard simple VHDL example
--	Version 1.0
--
--  Copyright (C) 2013 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
--
--  xflow -p xc7z020clg484-1 -synth xst_vhdl.opt slow_i2c.prj
--  xflow -p xc7z020clg484-1 -implement balanced.opt -config bitgen.opt slow_i2c.ngc
--  promgen -w -b -p bin -o slow_i2c.bin -u 0 slow_i2c.bit -data_width 32
--
--	assumes LM75 (or similar) on PMOD PB1
--	echo lm75 0x49 >/sys/class/i2c-adapter/i2c-0/new_device
--	cat /sys/class/i2c-adapter/i2c-0/0-0049/temp1_*
--
----------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;

entity top is
    port (
	swi	: in std_logic_vector(7 downto 0);	-- Switch: '1' is up
	--
	led	: out std_logic_vector(7 downto 0);	-- LED: '1' to turn on
	--
	pmod	: inout std_logic_vector(3 downto 0)	-- PMOD JB1/1-4
    );

    attribute LOC      : string;	-- Pin Location
    attribute IOSTANDARD : string;	-- LVTTL33, LVCMOS33 etc.
    attribute PERIOD : string;		-- clock period

    attribute LOC of swi: signal is "M15 H17 H18 H19 F21 H22 G22 F22";
    attribute IOSTANDARD of swi: signal is "LVCMOS33";

    attribute LOC of led: signal is "U14 U19 W22 V22 U21 U22 T21 T22";
    attribute IOSTANDARD of led: signal is "LVCMOS33";

    attribute LOC of pmod: signal is "W8 V10 W11 W12";
    attribute IOSTANDARD of pmod: signal is "LVCMOS33";

end entity top;


architecture RTL of top is
    component ps7_stub
	port (
	    i2c_sda_i : in std_ulogic;
	    i2c_sda_o : out std_ulogic;
	    i2c_sda_tn : out std_ulogic;
	    --
	    i2c_scl_i : in std_ulogic;
	    i2c_scl_o : out std_ulogic;
	    i2c_scl_tn : out std_ulogic
	);
    end component ps7_stub;

    component PULLUP
	port (
	    O : out std_ulogic := 'H'
	);
    end component PULLUP;

    component OBUF
	generic (
	    CAPACITANCE : string := "DONT_CARE";
	    DRIVE : integer := 12;
	    IOSTANDARD : string := "DEFAULT";
	    SLEW : string := "SLOW"
	);
	port (
	    O : out std_ulogic;
	    I : in std_ulogic
	);
    end component OBUF;

    component IOBUF
	generic (
	    CAPACITANCE : string := "DONT_CARE";
	    DRIVE : integer := 12;
	    IBUF_DELAY_VALUE : string := "0";
	    IBUF_LOW_PWR : boolean := TRUE;
	    IFD_DELAY_VALUE : string := "AUTO";
	    IOSTANDARD : string := "DEFAULT";
	    SLEW : string := "SLOW"
	);
	port (
	    O : out std_ulogic;
	    IO : inout std_ulogic;
	    I : in std_ulogic;
	    T : in std_ulogic
	);
    end component IOBUF;

    signal sda_i : std_ulogic;
    signal sda_o : std_ulogic;
    signal sda_tn : std_ulogic;
    signal sda_t : std_ulogic;

    signal scl_i : std_ulogic;
    signal scl_o : std_ulogic;
    signal scl_tn : std_ulogic;
    signal scl_t : std_ulogic;

    signal addr : std_logic_vector(1 downto 0);

    attribute buffer_type : string;	-- [io]buf[ghr][p]|none

begin
    ps7_stub_inst : ps7_stub
	port map ( i2c_sda_i => sda_i, i2c_sda_o => sda_o, i2c_sda_tn => sda_tn,
		   i2c_scl_i => scl_i, i2c_scl_o => scl_o, i2c_scl_tn => scl_tn );


    -- lm75 address
    addr <= swi(1 downto 0);
    GEN_BUF: for N in 0 to 1 generate
	OBUF_inst_0 : OBUF
	    generic map ( IOSTANDARD => "LVCMOS33" )
	    port map ( I => addr(N), O => pmod(N) );
	OBUF_inst_1 : OBUF
	    generic map ( IOSTANDARD => "LVCMOS33" )
	    port map ( I => addr(N), O => led(N) );
    end generate GEN_BUF;

    -- sda
    sda_t <= '1' when sda_tn = '0' else '0';
    IOBUF_0_inst : IOBUF
	generic map ( IOSTANDARD => "LVCMOS33" )
	port map ( I => sda_o, O => sda_i, T => sda_t, IO => pmod(2) );
    PULLUP_0_inst : PULLUP
	port map ( O => pmod(2) );

    -- scl
    scl_t <= '1' when scl_tn = '0' else '0';
    IOBUF_1_inst : IOBUF
	generic map ( IOSTANDARD => "LVCMOS33" )
	port map ( I => scl_o, O => scl_i, T => scl_t, IO => pmod(3) );
    PULLUP_1_inst : PULLUP
	port map ( O => pmod(3) );

    -- visual
    led(7 downto 5) <= (sda_i, sda_o, sda_t) xor swi(7 downto 5);
    led(4 downto 2) <= (scl_i, scl_o, scl_t) xor swi(4 downto 2);

end RTL;