---------------------------------------------------------------------------- -- top.vhd (for reg_pll) -- ZedBoard simple VHDL example -- Version 1.0 -- -- Copyright (C) 2013 H.Poetzl -- -- This program is free software: you can redistribute it and/or -- modify it under the terms of the GNU General Public License -- as published by the Free Software Foundation, either version -- 2 of the License, or (at your option) any later version. -- -- Vivado 2013.2: -- mkdir -p build.vivado -- (cd build.vivado; vivado -mode tcl -source ../vivado.tcl) -- (cd build.vivado; promgen -w -b -p bin -u 0 reg_pll.bit -data_width 32) ---------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.ALL; library unisim; use unisim.VCOMPONENTS.all; library unimacro; use unimacro.VCOMPONENTS.all; use work.axi3m_pkg.all; -- AXI3 Master use work.axi3ml_pkg.all; -- AXI3 Lite Master entity top is port ( clk_100 : in std_logic; -- input clock to FPGA -- swi : in std_logic_vector(7 downto 0); led : out std_logic_vector(7 downto 0) ); end entity top; architecture RTL of top is attribute KEEP_HIERARCHY : string; attribute KEEP_HIERARCHY of RTL : architecture is "TRUE"; attribute DONT_TOUCH : string; attribute MARK_DEBUG : string; -------------------------------------------------------------------- -- PS7 AXI Master Signals -------------------------------------------------------------------- signal m_axi1_aclk : std_logic; signal m_axi1_areset_n : std_logic; signal m_axi1_ri : axi3m_read_in_r; signal m_axi1_ro : axi3m_read_out_r; signal m_axi1_wi : axi3m_write_in_r; signal m_axi1_wo : axi3m_write_out_r; signal m_axi1l_ri : axi3ml_read_in_r; signal m_axi1l_ro : axi3ml_read_out_r; signal m_axi1l_wi : axi3ml_write_in_r; signal m_axi1l_wo : axi3ml_write_out_r; -------------------------------------------------------------------- -- PS7 Signals -------------------------------------------------------------------- signal ps_fclk : std_logic_vector(3 downto 0); signal ps_reset_n : std_logic_vector(3 downto 0); -------------------------------------------------------------------- -- PLL Signals -------------------------------------------------------------------- signal pll_clkout : std_logic_vector(5 downto 0); signal pll_clkin1 : std_ulogic; signal pll_clkin2 : std_ulogic; signal pll_clkinsel : std_ulogic; signal pll_fbout : std_ulogic; signal pll_fbin : std_ulogic; signal pll_locked : std_ulogic; signal pll_rst : std_ulogic; signal pll_dclk : std_ulogic; signal pll_den : std_ulogic; signal pll_dwe : std_ulogic; signal pll_drdy : std_ulogic; signal pll_daddr : std_logic_vector(6 downto 0); signal pll_do : std_logic_vector(15 downto 0); signal pll_di : std_logic_vector(15 downto 0); signal pll_pwrdwn : std_ulogic; begin -------------------------------------------------------------------- -- PS7 Interface -------------------------------------------------------------------- ps7_stub_inst : entity work.ps7_stub port map ( ps_fclk => ps_fclk, ps_reset_n => ps_reset_n, -- m_axi1_aclk => m_axi1_aclk, m_axi1_areset_n => m_axi1_areset_n, -- m_axi1_arid => m_axi1_ro.arid, m_axi1_araddr => m_axi1_ro.araddr, m_axi1_arburst => m_axi1_ro.arburst, m_axi1_arlen => m_axi1_ro.arlen, m_axi1_arsize => m_axi1_ro.arsize, m_axi1_arprot => m_axi1_ro.arprot, m_axi1_arvalid => m_axi1_ro.arvalid, m_axi1_arready => m_axi1_ri.arready, -- m_axi1_rid => m_axi1_ri.rid, m_axi1_rdata => m_axi1_ri.rdata, m_axi1_rlast => m_axi1_ri.rlast, m_axi1_rresp => m_axi1_ri.rresp, m_axi1_rvalid => m_axi1_ri.rvalid, m_axi1_rready => m_axi1_ro.rready, -- m_axi1_awid => m_axi1_wo.awid, m_axi1_awaddr => m_axi1_wo.awaddr, m_axi1_awburst => m_axi1_wo.awburst, m_axi1_awlen => m_axi1_wo.awlen, m_axi1_awsize => m_axi1_wo.awsize, m_axi1_awprot => m_axi1_wo.awprot, m_axi1_awvalid => m_axi1_wo.awvalid, m_axi1_awready => m_axi1_wi.wready, -- m_axi1_wid => m_axi1_wo.wid, m_axi1_wdata => m_axi1_wo.wdata, m_axi1_wstrb => m_axi1_wo.wstrb, m_axi1_wlast => m_axi1_wo.wlast, m_axi1_wvalid => m_axi1_wo.wvalid, m_axi1_wready => m_axi1_wi.wready, -- m_axi1_bid => m_axi1_wi.bid, m_axi1_bresp => m_axi1_wi.bresp, m_axi1_bvalid => m_axi1_wi.bvalid, m_axi1_bready => m_axi1_wo.bready ); m_axi1_aclk <= clk_100; -------------------------------------------------------------------- -- AXI3 Interconnect -------------------------------------------------------------------- axi_lite_inst : entity work.axi_lite port map ( s_axi_aclk => m_axi1_aclk, s_axi_areset_n => m_axi1_areset_n, s_axi_ro => m_axi1_ri, s_axi_ri => m_axi1_ro, s_axi_wo => m_axi1_wi, s_axi_wi => m_axi1_wo, m_axi_ro => m_axi1l_ro, m_axi_ri => m_axi1l_ri, m_axi_wo => m_axi1l_wo, m_axi_wi => m_axi1l_wi ); -------------------------------------------------------------------- -- PLL -------------------------------------------------------------------- pll_inst : PLLE2_ADV generic map ( BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW CLKFBOUT_MULT => 10, -- Multiply value (2-64) CLKFBOUT_PHASE => 0.0, -- Phase offset (-360.000-360.000). -- CLKIN1_PERIOD => 10.0, CLKIN2_PERIOD => 10.0, -- CLKOUT0_DIVIDE => 1, -- (1-128) CLKOUT1_DIVIDE => 2, CLKOUT2_DIVIDE => 3, CLKOUT3_DIVIDE => 4, CLKOUT4_DIVIDE => 5, CLKOUT5_DIVIDE => 6, -- CLKOUT0_DUTY_CYCLE => 0.5, -- (0.001-0.999) CLKOUT1_DUTY_CYCLE => 0.5, CLKOUT2_DUTY_CYCLE => 0.5, CLKOUT3_DUTY_CYCLE => 0.5, CLKOUT4_DUTY_CYCLE => 0.5, CLKOUT5_DUTY_CYCLE => 0.5, -- CLKOUT0_PHASE => 0.0, -- (-360.000-360.000) CLKOUT1_PHASE => 0.0, CLKOUT2_PHASE => 0.0, CLKOUT3_PHASE => 0.0, CLKOUT4_PHASE => 0.0, CLKOUT5_PHASE => 0.0, -- COMPENSATION => "ZHOLD", -- ZHOLD, BUF_IN, EXTERNAL, INTERNAL DIVCLK_DIVIDE => 1, -- Master division value (1-56) -- REF_JITTER1 => 0.0, -- Jitter in UI (0.000-0.999) REF_JITTER2 => 0.0, -- STARTUP_WAIT => "FALSE" ) port map ( CLKIN1 => pll_clkin1, CLKIN2 => pll_clkin2, CLKINSEL => pll_clkinsel, -- CLKOUT0 => pll_clkout(0), CLKOUT1 => pll_clkout(1), CLKOUT2 => pll_clkout(2), CLKOUT3 => pll_clkout(3), CLKOUT4 => pll_clkout(4), CLKOUT5 => pll_clkout(5), -- CLKFBOUT => pll_fbout, CLKFBIN => pll_fbin, -- LOCKED => pll_locked, -- RST => pll_rst, -- DCLK => pll_dclk, DEN => pll_den, DWE => pll_dwe, DRDY => pll_drdy, -- DADDR => pll_daddr, DO => pll_do, DI => pll_di, -- PWRDWN => pll_pwrdwn ); pll_rst <= swi(0) or not ps_reset_n(0); pll_fbin <= pll_fbout; pll_clkin1 <= clk_100; pll_clkin2 <= ps_fclk(0); pll_clkinsel <= swi(1) xor ps_reset_n(1); pll_pwrdwn <= swi(2); reg_pll_inst : entity work.reg_pll port map ( s_axi_aclk => m_axi1_aclk, s_axi_areset_n => m_axi1_areset_n, -- s_axi_ro => m_axi1l_ri, s_axi_ri => m_axi1l_ro, s_axi_wo => m_axi1l_wi, s_axi_wi => m_axi1l_wo, -- pll_dclk => pll_dclk, pll_den => pll_den, pll_dwe => pll_dwe, pll_drdy => pll_drdy, -- pll_daddr => pll_daddr, pll_dout => pll_do, pll_din => pll_di ); -------------------------------------------------------------------- -- LED Status output -------------------------------------------------------------------- led(7) <= pll_locked; GEN_DIV: for I in 6 downto 0 generate begin FBOUT : if I = 6 generate div_inst : entity work.async_div generic map ( STAGES => 28 ) port map ( clk_in => pll_fbout, reset => swi(3), clk_out => led(I) ); end generate; CLKOUT : if I < 6 generate div_inst : entity work.async_div generic map ( STAGES => 28 ) port map ( clk_in => pll_clkout(I), reset => swi(3), clk_out => led(I) ); end generate; end generate; end RTL;