---------------------------------------------------------------------------- -- reg_file.vhd -- ZedBoard simple VHDL example -- Version 1.0 -- -- Copyright (C) 2013 H.Poetzl -- -- This program is free software: you can redistribute it and/or -- modify it under the terms of the GNU General Public License -- as published by the Free Software Foundation, either version -- 2 of the License, or (at your option) any later version. -- -- xflow -p xc7z020clg484-1 -synth xst_vhdl.opt reg_file.prj -- xflow -p xc7z020clg484-1 -implement balanced.opt -config bitgen.opt reg_file.ngc -- promgen -w -b -p bin -o reg_file.bin -u 0 reg_file.bit -data_width 32 -- -- 0xe000a010 rw ps7::gpio::MASK_DATA_2_LSW -- 0xe000a048 rw ps7::gpio::DATA_2 -- 0xe000a068 ro ps7::gpio::DATA_2_RO -- 0xe000a284 rw ps7::gpio::DIRM_2 -- 0xe000a288 rw ps7::gpio::OEN_2 -- -- ... and similar for *_3 -- -- 0xf8000900 rw ps7::slcr::LVL_SHFTR_EN -- ---------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.ALL; entity reg_file is generic ( REG_SIZE : integer := 32 ); port ( latch : in std_logic; index : in std_logic_vector(3 downto 0); value : in std_logic_vector(REG_SIZE - 1 downto 0); -- reg_0 : out std_logic_vector(REG_SIZE - 1 downto 0); reg_1 : out std_logic_vector(REG_SIZE - 1 downto 0); reg_2 : out std_logic_vector(REG_SIZE - 1 downto 0); reg_3 : out std_logic_vector(REG_SIZE - 1 downto 0); reg_4 : out std_logic_vector(REG_SIZE - 1 downto 0); reg_5 : out std_logic_vector(REG_SIZE - 1 downto 0); reg_6 : out std_logic_vector(REG_SIZE - 1 downto 0); reg_7 : out std_logic_vector(REG_SIZE - 1 downto 0); reg_8 : out std_logic_vector(REG_SIZE - 1 downto 0); reg_9 : out std_logic_vector(REG_SIZE - 1 downto 0) ); end entity reg_file; architecture RTL of reg_file is signal val_0 : std_logic_vector(REG_SIZE - 1 downto 0) := X"12345678"; signal val_1 : std_logic_vector(REG_SIZE - 1 downto 0); signal val_2 : std_logic_vector(REG_SIZE - 1 downto 0); signal val_3 : std_logic_vector(REG_SIZE - 1 downto 0); signal val_4 : std_logic_vector(REG_SIZE - 1 downto 0); signal val_5 : std_logic_vector(REG_SIZE - 1 downto 0); signal val_6 : std_logic_vector(REG_SIZE - 1 downto 0); signal val_7 : std_logic_vector(REG_SIZE - 1 downto 0); signal val_8 : std_logic_vector(REG_SIZE - 1 downto 0); signal val_9 : std_logic_vector(REG_SIZE - 1 downto 0); begin reg_proc : process(latch, index, value) variable idx : natural; begin idx := to_integer(unsigned(index)); if rising_edge(latch) then case idx is when 0 => val_0 <= value; when 1 => val_1 <= value; when 2 => val_2 <= value; when 3 => val_3 <= value; when 4 => val_4 <= value; when 5 => val_5 <= value; when 6 => val_6 <= value; when 7 => val_7 <= value; when 8 => val_8 <= value; when 9 => val_9 <= value; when others => null; end case; end if; end process; reg_0 <= val_0; reg_1 <= val_1; reg_2 <= val_2; reg_3 <= val_3; reg_4 <= val_4; reg_5 <= val_5; reg_6 <= val_6; reg_7 <= val_7; reg_8 <= val_8; reg_9 <= val_9; end RTL; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.ALL; entity top is port ( swi : in std_logic_vector(7 downto 0); -- Switch: '1' is up -- led : out std_logic_vector(7 downto 0) -- LED: '1' to turn on ); attribute LOC : string; -- Pin Location attribute IOSTANDARD : string; -- LVTTL33, LVCMOS33 etc. attribute PERIOD : string; -- clock period attribute LOC of swi: signal is "M15 H17 H18 H19 F21 H22 G22 F22"; attribute IOSTANDARD of swi: signal is "LVCMOS33"; attribute LOC of led: signal is "U14 U19 W22 V22 U21 U22 T21 T22"; attribute IOSTANDARD of led: signal is "LVCMOS33"; end entity top; architecture RTL of top is component ps7_stub port ( gpio_o : out std_logic_vector(63 downto 0) ); end component ps7_stub; component reg_file generic ( REG_SIZE : integer := 32 ); port ( latch : in std_logic; index : in std_logic_vector(3 downto 0); value : in std_logic_vector(REG_SIZE - 1 downto 0); -- reg_0 : out std_logic_vector(REG_SIZE - 1 downto 0); reg_1 : out std_logic_vector(REG_SIZE - 1 downto 0); reg_2 : out std_logic_vector(REG_SIZE - 1 downto 0); reg_3 : out std_logic_vector(REG_SIZE - 1 downto 0); reg_4 : out std_logic_vector(REG_SIZE - 1 downto 0); reg_5 : out std_logic_vector(REG_SIZE - 1 downto 0); reg_6 : out std_logic_vector(REG_SIZE - 1 downto 0); reg_7 : out std_logic_vector(REG_SIZE - 1 downto 0); reg_8 : out std_logic_vector(REG_SIZE - 1 downto 0); reg_9 : out std_logic_vector(REG_SIZE - 1 downto 0) ); end component reg_file; signal gpio_o : std_logic_vector(63 downto 0); attribute buffer_type : string; -- [io]buf[ghr][p]|none attribute buffer_type of gpio_o: signal is "bufg"; signal reg_0 : std_logic_vector(31 downto 0); signal reg_1 : std_logic_vector(31 downto 0); signal reg_2 : std_logic_vector(31 downto 0); signal reg_3 : std_logic_vector(31 downto 0); signal reg_4 : std_logic_vector(31 downto 0); signal reg_5 : std_logic_vector(31 downto 0); signal reg_6 : std_logic_vector(31 downto 0); signal reg_7 : std_logic_vector(31 downto 0); signal reg_8 : std_logic_vector(31 downto 0); signal reg_9 : std_logic_vector(31 downto 0); begin ps7_stub_inst : ps7_stub port map ( gpio_o => gpio_o ); reg_file_inst : reg_file port map ( latch => gpio_o(36), index => gpio_o(35 downto 32), value => gpio_o(31 downto 0), reg_0 => reg_0, reg_1 => reg_1, reg_2 => reg_2, reg_3 => reg_3, reg_4 => reg_4, reg_5 => reg_5, reg_6 => reg_6, reg_7 => reg_7, reg_8 => reg_8, reg_9 => reg_9 ); vis_proc : process(swi, reg_0, reg_1, reg_2, reg_3, reg_4, reg_5, reg_6, reg_7, reg_8, reg_9) variable idx, pos : natural; begin idx := to_integer(unsigned(swi(3 downto 0))); pos := to_integer(unsigned(swi(7 downto 6))) * 8; case idx is when 0 => led <= reg_0(pos + 7 downto pos); when 1 => led <= reg_1(pos + 7 downto pos); when 2 => led <= reg_2(pos + 7 downto pos); when 3 => led <= reg_3(pos + 7 downto pos); when 4 => led <= reg_4(pos + 7 downto pos); when 5 => led <= reg_5(pos + 7 downto pos); when 6 => led <= reg_6(pos + 7 downto pos); when 7 => led <= reg_7(pos + 7 downto pos); when 8 => led <= reg_8(pos + 7 downto pos); when 9 => led <= reg_9(pos + 7 downto pos); when others => led <= swi; end case; end process; end RTL;