---------------------------------------------------------------------------- -- reg_file.vhd -- ZedBoard simple VHDL example -- Version 1.0 -- -- Copyright (C) 2013 H.Poetzl -- -- This program is free software: you can redistribute it and/or -- modify it under the terms of the GNU General Public License -- as published by the Free Software Foundation, either version -- 2 of the License, or (at your option) any later version. -- -- xflow -p xc7z020clg484-1 -wd build -synth xst_vhdl.opt reg_file.prj -- xflow -p xc7z020clg484-1 -wd build -implement balanced.opt -config bitgen.opt reg_file.ngc -- promgen -w -b -p bin -o reg_file.bin -u 0 reg_file.bit -data_width 32 -- -- 0xf8000900 rw ps7::slcr::LVL_SHFTR_EN -- ---------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.ALL; library axi_lite_ipif_v1_01_a; use axi_lite_ipif_v1_01_a.axi_lite_ipif; entity reg_file is generic ( REG_SIZE : integer := 32 ); port ( s_axi_aclk : in std_logic; -- s_axi_aresetn : in std_logic; -- write address s_axi_awaddr : in std_logic_vector(31 downto 0); s_axi_awvalid : in std_logic; s_axi_awready : out std_logic; -- write data s_axi_wdata : in std_logic_vector(31 downto 0); s_axi_wstrb : in std_logic_vector(3 downto 0); s_axi_wvalid : in std_logic; s_axi_wready : out std_logic; -- write response s_axi_bresp : out std_logic_vector(1 downto 0); s_axi_bvalid : out std_logic; s_axi_bready : in std_logic; -- read address s_axi_araddr : in std_logic_vector(31 downto 0); s_axi_arvalid : in std_logic; s_axi_arready : out std_logic; -- read data s_axi_rdata : out std_logic_vector(31 downto 0); s_axi_rresp : out std_logic_vector(1 downto 0); s_axi_rvalid : out std_logic; s_axi_rready : in std_logic; -- reg_0 : out std_logic_vector(REG_SIZE - 1 downto 0); reg_1 : out std_logic_vector(REG_SIZE - 1 downto 0); reg_2 : out std_logic_vector(REG_SIZE - 1 downto 0); reg_3 : out std_logic_vector(REG_SIZE - 1 downto 0); reg_4 : out std_logic_vector(REG_SIZE - 1 downto 0); reg_5 : out std_logic_vector(REG_SIZE - 1 downto 0); reg_6 : out std_logic_vector(REG_SIZE - 1 downto 0); reg_7 : out std_logic_vector(REG_SIZE - 1 downto 0); reg_8 : out std_logic_vector(REG_SIZE - 1 downto 0); reg_9 : out std_logic_vector(REG_SIZE - 1 downto 0) ); end entity reg_file; architecture RTL of reg_file is signal val_0 : std_logic_vector(REG_SIZE - 1 downto 0) := X"12345678"; signal val_1 : std_logic_vector(REG_SIZE - 1 downto 0); signal val_2 : std_logic_vector(REG_SIZE - 1 downto 0); signal val_3 : std_logic_vector(REG_SIZE - 1 downto 0); signal val_4 : std_logic_vector(REG_SIZE - 1 downto 0); signal val_5 : std_logic_vector(REG_SIZE - 1 downto 0); signal val_6 : std_logic_vector(REG_SIZE - 1 downto 0); signal val_7 : std_logic_vector(REG_SIZE - 1 downto 0); signal val_8 : std_logic_vector(REG_SIZE - 1 downto 0); signal val_9 : std_logic_vector(REG_SIZE - 1 downto 0); signal bus2ip_clk : std_logic; signal bus2ip_resetn : std_logic; -- signal bus2ip_addr : std_logic_vector(31 downto 0); signal bus2ip_data : std_logic_vector(31 downto 0); signal bus2ip_rnw : std_logic; signal bus2ip_be : std_logic_vector(3 downto 0); signal bus2ip_cs : std_logic_vector(0 downto 0); signal bus2ip_rce : std_logic_vector(9 downto 0); signal bus2ip_wce : std_logic_vector(9 downto 0); signal ip2bus_data : std_logic_vector(31 downto 0); signal ip2bus_wack : std_logic; signal ip2bus_rack : std_logic; signal ip2bus_error : std_logic; begin ------------------------------------------ -- instantiate axi_lite_ipif ------------------------------------------ AXI_LITE_IPIF_inst : entity axi_lite_ipif_v1_01_a.axi_lite_ipif generic map ( C_S_AXI_DATA_WIDTH => 32, C_S_AXI_ADDR_WIDTH => 32, C_S_AXI_MIN_SIZE => X"000001FF", C_USE_WSTRB => 0, C_DPHASE_TIMEOUT => 8, C_ARD_ADDR_RANGE_ARRAY => ( X"0000_0000_6000_0000", X"0000_0000_6000_0FFF" ), C_ARD_NUM_CE_ARRAY => ( 0 => (10) ), C_FAMILY => "zynq" ) port map ( S_AXI_ACLK => s_axi_aclk, S_AXI_ARESETN => s_axi_aresetn, S_AXI_AWADDR => s_axi_awaddr, S_AXI_AWVALID => s_axi_awvalid, S_AXI_WDATA => s_axi_wdata, S_AXI_WSTRB => s_axi_wstrb, S_AXI_WVALID => s_axi_wvalid, S_AXI_BREADY => s_axi_bready, S_AXI_ARADDR => s_axi_araddr, S_AXI_ARVALID => s_axi_arvalid, S_AXI_RREADY => s_axi_rready, S_AXI_ARREADY => s_axi_arready, S_AXI_RDATA => s_axi_rdata, S_AXI_RRESP => s_axi_rresp, S_AXI_RVALID => s_axi_rvalid, S_AXI_WREADY => s_axi_wready, S_AXI_BRESP => s_axi_bresp, S_AXI_BVALID => s_axi_bvalid, S_AXI_AWREADY => s_axi_awready, -- Bus2IP_Clk => bus2ip_clk, Bus2IP_Resetn => bus2ip_resetn, Bus2IP_Addr => bus2ip_addr, Bus2IP_RNW => bus2ip_rnw, Bus2IP_BE => bus2ip_be, Bus2IP_CS => bus2ip_cs, Bus2IP_RdCE => bus2ip_rce, Bus2IP_WrCE => bus2ip_wce, Bus2IP_Data => bus2ip_data, -- IP2Bus_WrAck => ip2bus_wack, IP2Bus_RdAck => ip2bus_rack, IP2Bus_Error => ip2bus_error, IP2Bus_Data => ip2bus_data ); reg_write_proc : process(bus2ip_clk, bus2ip_wce, val_0, val_1, val_2, val_3, val_4, val_5, val_6, val_7, val_8, val_9) begin if rising_edge(bus2ip_clk) then if bus2ip_resetn = '0' then val_0 <= (others => '0'); val_1 <= (others => '0'); val_2 <= (others => '0'); val_3 <= (others => '0'); val_4 <= (others => '0'); val_5 <= (others => '0'); val_6 <= (others => '0'); val_7 <= (others => '0'); val_8 <= (others => '0'); val_9 <= (others => '0'); else case bus2ip_wce is when "1000000000" => val_0 <= bus2ip_data; when "0100000000" => val_1 <= bus2ip_data; when "0010000000" => val_2 <= bus2ip_data; when "0001000000" => val_3 <= bus2ip_data; when "0000100000" => val_4 <= bus2ip_data; when "0000010000" => val_5 <= bus2ip_data; when "0000001000" => val_6 <= bus2ip_data; when "0000000100" => val_7 <= bus2ip_data; when "0000000010" => val_8 <= bus2ip_data; when "0000000001" => val_9 <= bus2ip_data; when others => null; end case; end if; end if; if bus2ip_wce = "0000000000" then ip2bus_wack <= '0'; else ip2bus_wack <= '1'; end if; end process; reg_read_proc : process(bus2ip_clk, bus2ip_rce, val_0, val_1, val_2, val_3, val_4, val_5, val_6, val_7, val_8, val_9) begin case bus2ip_rce is when "1000000000" => ip2bus_data <= val_0; when "0100000000" => ip2bus_data <= val_1; when "0010000000" => ip2bus_data <= val_2; when "0001000000" => ip2bus_data <= val_3; when "0000100000" => ip2bus_data <= val_4; when "0000010000" => ip2bus_data <= val_5; when "0000001000" => ip2bus_data <= val_6; when "0000000100" => ip2bus_data <= val_7; when "0000000010" => ip2bus_data <= val_8; when "0000000001" => ip2bus_data <= val_9; when others => ip2bus_data <= (others => '1'); end case; if bus2ip_rce = "0000000000" then ip2bus_rack <= '0'; else ip2bus_rack <= '1'; end if; end process; reg_0 <= val_0; reg_1 <= val_1; reg_2 <= val_2; reg_3 <= val_3; reg_4 <= val_4; reg_5 <= val_5; reg_6 <= val_6; reg_7 <= val_7; reg_8 <= val_8; reg_9 <= val_9; ip2bus_error <= '0'; end RTL;