----------------------------------------------------------------------------
--  top.vhd
--	ZedBoard simple VHDL example
--	Version 1.0
--
--  Copyright (C) 2013 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
--
--  Vivado 2013.2:
--    mkdir -p build.vivado
--    (cd build.vivado; vivado -mode tcl -source ../vivado.tcl)
--
--  0xf8000900 rw	ps7::slcr::LVL_SHFTR_EN
----------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.ALL;


entity top is
    port (
	DDR_Addr : inout std_logic_vector(14 downto 0);
	DDR_BankAddr : inout std_logic_vector(2 downto 0);
	DDR_Clk : inout std_ulogic;
	DDR_Clk_n : inout std_ulogic;
	DDR_CAS_n : inout std_ulogic;
	DDR_RAS_n : inout std_ulogic;
	DDR_CKE : inout std_ulogic;
	DDR_CS_n : inout std_ulogic;
	DDR_DM : inout std_logic_vector(3 downto 0);
	DDR_DQ : inout std_logic_vector(31 downto 0);
	DDR_DQS_n : inout std_logic_vector(3 downto 0);
	DDR_DQS : inout std_logic_vector(3 downto 0);
	DDR_DRSTB : inout std_ulogic;
	DDR_ODT : inout std_ulogic;
	DDR_VR_n : inout std_ulogic;
	DDR_VR : inout std_ulogic;
	DDR_WEB : inout std_ulogic;
	--
	MIO : inout std_logic_vector(53 downto 0);
	--
	PS_CLK : inout std_ulogic;
	PS_PORB : inout std_ulogic;
	PS_SRSTB : inout std_ulogic;
	--
	clk_100 : in std_logic;				-- input clock to FPGA
	--
	btn_c	: in std_logic;				-- Button: '1' is pressed
	swi	: in std_logic_vector(7 downto 0);	-- Switch: '1' is up
	--
	led	: out std_logic_vector(7 downto 0)	-- LED: '1' to turn on
    );

end entity top;


architecture RTL of top is

    signal m_axi_aclk : std_logic;
    signal m_axi_aresetn : std_logic;

    signal m_axi_awid : std_logic_vector(11 downto 0);
    signal m_axi_awaddr : std_logic_vector(31 downto 0);
    signal m_axi_awvalid : std_logic;
    signal m_axi_awready : std_logic;

    signal m_axi_wdata : std_logic_vector(31 downto 0);
    signal m_axi_wstrb : std_logic_vector(3 downto 0);
    signal m_axi_wlast : std_logic;
    signal m_axi_wvalid : std_logic;
    signal m_axi_wready : std_logic;

    signal m_axi_bid : std_logic_vector(11 downto 0);
    signal m_axi_bresp : std_logic_vector(1 downto 0);
    signal m_axi_bvalid : std_logic;
    signal m_axi_bready : std_logic;

    signal m_axi_arid : std_logic_vector(11 downto 0);
    signal m_axi_araddr : std_logic_vector(31 downto 0);
    signal m_axi_arvalid : std_logic;
    signal m_axi_arready : std_logic;

    signal m_axi_rid : std_logic_vector(11 downto 0);
    signal m_axi_rdata : std_logic_vector(31 downto 0);
    signal m_axi_rresp : std_logic_vector(1 downto 0);
    signal m_axi_rvalid : std_logic;
    signal m_axi_rready : std_logic;

    signal bram_addr : std_logic_vector(14 downto 5);
    signal bram_data : std_logic_vector(31 downto 0);

begin
    ps7_stub_inst : entity work.ps7_stub
    port map (
	ddr_addr => DDR_Addr,
	ddr_bankaddr => DDR_BankAddr,
	ddr_cas_n => DDR_CAS_n,
	ddr_cke => DDR_CKE,
	ddr_clk => DDR_Clk,
	ddr_clk_n => DDR_Clk_n,
	ddr_cs_n => DDR_CS_n,
	ddr_dm => DDR_DM,
	ddr_dq => DDR_DQ,
	ddr_dqs_n => DDR_DQS_n,
	ddr_dqs => DDR_DQS,
	ddr_drstb => DDR_DRSTB,
	ddr_odt => DDR_ODT,
	ddr_ras_n => DDR_RAS_n,
	ddr_vr_n => DDR_VR_n,
	ddr_vr => DDR_VR,
	ddr_web => DDR_WEB,
	--
	ps_mio => MIO,
	ps_clk => PS_CLK,
	ps_porb => PS_PORB,
	ps_srstb => PS_SRSTB,

	m_axi_aclk => m_axi_aclk,

	m_axi_aresetn => m_axi_aresetn,

	m_axi_awid => m_axi_awid,
	m_axi_awaddr => m_axi_awaddr,
	m_axi_awvalid => m_axi_awvalid,
	m_axi_awready => m_axi_awready,

	m_axi_wdata => m_axi_wdata,
	m_axi_wstrb => m_axi_wstrb,
	m_axi_wlast => m_axi_wlast,
	m_axi_wvalid => m_axi_wvalid,
	m_axi_wready => m_axi_wready,

	m_axi_bid => m_axi_bid,
	m_axi_bresp => m_axi_bresp,
	m_axi_bvalid => m_axi_bvalid,
	m_axi_bready => m_axi_bready,

	m_axi_arid => m_axi_arid,
	m_axi_araddr => m_axi_araddr,
	m_axi_arvalid => m_axi_arvalid,
	m_axi_arready => m_axi_arready,

	m_axi_rid => m_axi_rid,
	m_axi_rdata => m_axi_rdata,
	m_axi_rresp => m_axi_rresp,
	m_axi_rvalid => m_axi_rvalid,
	m_axi_rready => m_axi_rready );

    reg_bram_inst : entity work.reg_bram
    port map (
	m_axi_aclk => m_axi_aclk,
	m_axi_aresetn => m_axi_aresetn,

	m_axi_awid => m_axi_awid,
	m_axi_awaddr => m_axi_awaddr,
	m_axi_awvalid => m_axi_awvalid,
	m_axi_awready => m_axi_awready,

	m_axi_wdata => m_axi_wdata,
	m_axi_wstrb => m_axi_wstrb,
	m_axi_wlast => m_axi_wlast,
	m_axi_wvalid => m_axi_wvalid,
	m_axi_wready => m_axi_wready,

	m_axi_bid => m_axi_bid,
	m_axi_bresp => m_axi_bresp,
	m_axi_bvalid => m_axi_bvalid,
	m_axi_bready => m_axi_bready,

	m_axi_arid => m_axi_arid,
	m_axi_araddr => m_axi_araddr,
	m_axi_arvalid => m_axi_arvalid,
	m_axi_arready => m_axi_arready,

	m_axi_rid => m_axi_rid,
	m_axi_rdata => m_axi_rdata,
	m_axi_rresp => m_axi_rresp,
	m_axi_rvalid => m_axi_rvalid,
	m_axi_rready => m_axi_rready,

	bram_clk => clk_100,
	bram_addr => bram_addr,
	bram_din => (others => '1'),
	bram_dout => bram_data,
	bram_pin => (others => '0'),
	bram_pout => open,
	bram_en => '1',
	bram_ce => '1',
	bram_we => btn_c );

    m_axi_aclk <= clk_100;

    bram_addr(14 downto 13) <= "00";
    bram_addr(12 downto 5) <= swi;
    led <= bram_data(7 downto 0);

end RTL;