----------------------------------------------------------------------------
--  testbench.vhd
--	ZedBoard simple VHDL example
--	Version 1.0
--
--  Copyright (C) 2013 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
--
----------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.ALL;


entity testbench is
end entity testbench;


architecture RTL of testbench is

    signal clk_100 : std_logic;
    signal btn_c : std_logic;

    signal led : std_logic_vector(7 downto 0);


begin

    uut : entity work.pll
	port map ( clk_100 => clk_100, 	btn_c => btn_c, led => led );


    clk_100_proc : process
    begin
	clk_100 <= '1';
	wait for 5ns;
	clk_100 <= '0';
	wait for 5ns;
    end process;

    btn_c_proc : process
    begin
	btn_c <= '0';
	wait for 100ns;
	btn_c <= '1';
	wait for 500ns;
	btn_c <= '0';
	wait;
    end process;

end RTL;