----------------------------------------------------------------------------
--  pll.vhd
--	ZedBoard simple VHDL example
--	Version 1.0
--
--  Copyright (C) 2013 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
--
--  xflow -p xc7z020clg484-1 -wd build -synth xst_mixed.opt pll.prj
--  ln -s ../pll.ucf build/ # work around xflow bug
--  xflow -p xc7z020clg484-1 -wd build -implement balanced.opt -config bitgen.opt pll.ngc
--  (mkdir -p fuse; cd fuse; fuse testbench -prj ../pll.prj -o isim.elf)
--  (cd fuse; ./isim.elf -gui)
----------------------------------------------------------------------------



library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.ALL;

entity divider is
    generic (
	RATIO : integer := 10000000
    );
    port (
	clk_in	: in std_logic;		-- input clock
	--
	enable	: in std_logic;		-- enable divider
	--
	clk_out	: out std_logic		-- output clk_in
    );
end entity divider;

architecture RTL of divider is
begin
    divide_proc : process(clk_in, enable)
    variable count : integer range 0 to RATIO - 1;
    begin
	if enable = '0' then		-- reset
	    count := 0;
	elsif rising_edge(clk_in) then	-- clk
	    if count = RATIO - 1 then
	    	count := 0;
	    else
	    	count := count + 1;
	    end if;
	end if;
	
	if count < RATIO / 2 then
	    clk_out <= '0';
	else
	    clk_out <= '1';
	end if;
    end process;
end RTL;



library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.ALL;

library UNISIM;
use UNISIM.VComponents.all;


entity pll is
    port (
	clk_100 : in std_logic;		-- input clock to FPGA
	--
	btn_c	: in std_logic;		-- button 'center', '1' is pressed
	--
	led	: out std_logic_vector(7 downto 0)	-- LED: '1' to turn on
    );

end entity pll;


architecture RTL of pll is

    component PLLE2_BASE
	generic (
	    BANDWIDTH : string := "OPTIMIZED";
	    CLKFBOUT_MULT : integer := 5;
	    CLKFBOUT_PHASE : real := 0.000;
	    CLKIN1_PERIOD : real := 0.000;
	    CLKOUT0_DIVIDE : integer := 1;
	    CLKOUT0_DUTY_CYCLE : real := 0.500;
	    CLKOUT0_PHASE : real := 0.000;
	    CLKOUT1_DIVIDE : integer := 1;
	    CLKOUT1_DUTY_CYCLE : real := 0.500;
	    CLKOUT1_PHASE : real := 0.000;
	    CLKOUT2_DIVIDE : integer := 1;
	    CLKOUT2_DUTY_CYCLE : real := 0.500;
	    CLKOUT2_PHASE : real := 0.000;
	    CLKOUT3_DIVIDE : integer := 1;
	    CLKOUT3_DUTY_CYCLE : real := 0.500;
	    CLKOUT3_PHASE : real := 0.000;
	    CLKOUT4_DIVIDE : integer := 1;
	    CLKOUT4_DUTY_CYCLE : real := 0.500;
	    CLKOUT4_PHASE : real := 0.000;
	    CLKOUT5_DIVIDE : integer := 1;
	    CLKOUT5_DUTY_CYCLE : real := 0.500;
	    CLKOUT5_PHASE : real := 0.000;
	    DIVCLK_DIVIDE : integer := 1;
	    REF_JITTER1 : real := 0.010;
	    STARTUP_WAIT : string := "FALSE"
	);
	port (
	    CLKFBOUT : out std_ulogic;
	    CLKOUT0 : out std_ulogic;
	    CLKOUT1 : out std_ulogic;
	    CLKOUT2 : out std_ulogic;
	    CLKOUT3 : out std_ulogic;
	    CLKOUT4 : out std_ulogic;
	    CLKOUT5 : out std_ulogic;
	    LOCKED : out std_ulogic;
	    CLKFBIN : in std_ulogic;
	    CLKIN1 : in std_ulogic;
	    PWRDWN : in std_ulogic;
	    RST : in std_ulogic
	);
    end component PLLE2_BASE;

    signal pll_fb : std_logic;
    signal pll_locked : std_logic;
    signal pll_clk : std_logic_vector(5 downto 0);

    signal enable : std_logic;

begin
    ps7_stub_inst : entity work.ps7_stub;

    pll_inst : PLLE2_BASE
	generic map (
	    CLKIN1_PERIOD => 10.0,	-- 100MHz = 10ns
	    CLKFBOUT_MULT => 9,		-- 100MHz x 9 = 900MHz
	    CLKOUT0_DIVIDE => 25,	-- 36MHz
	    CLKOUT1_DIVIDE => 20,	-- 45MHz
	    CLKOUT2_DIVIDE => 18,	-- 50MHz
	    CLKOUT3_DIVIDE => 15,	-- 60MHz
	    CLKOUT4_DIVIDE => 12,	-- 75MHz
	    CLKOUT5_DIVIDE => 10,	-- 90MHz
	    DIVCLK_DIVIDE => 1 )
	port map ( 
	    CLKIN1 => clk_100,

	    CLKFBOUT => pll_fb,
	    CLKFBIN => pll_fb,

	    CLKOUT0 => pll_clk(0),
	    CLKOUT1 => pll_clk(1),
	    CLKOUT2 => pll_clk(2),
	    CLKOUT3 => pll_clk(3),
	    CLKOUT4 => pll_clk(4),
	    CLKOUT5 => pll_clk(5),

	    LOCKED => pll_locked,
	    PWRDWN => '0',
	    RST => '0' );


    div_inst_100 : entity work.divider
	port map ( clk_in => clk_100,
	    enable => btn_c, clk_out => led(6));

    gen_div : for I in 0 to 5 generate
	div_inst : entity work.divider
	    port map ( clk_in => pll_clk(I),
		enable => btn_c, clk_out => led(I));
    end generate;

    led(7) <= pll_locked;

end RTL;