----------------------------------------------------------------------------
--  logic.vhd
--	ZedBoard simple VHDL example
--	Version 1.0
--
--  Copyright (C) 2013 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
--
--  xflow -p xc7z020clg484-1 -wd build -synth xst_vhdl.opt logic.prj
--  xflow -p xc7z020clg484-1 -wd build -implement balanced.opt -config bitgen.opt logic.ngc
--  (cd build; promgen -w -b -p bin -o logic.bin -u 0 logic.bit -data_width 32)
--
----------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.ALL;

entity top is
    port (
	clk_100 : in std_logic;		-- input clock to FPGA
	--
	swi	: in std_logic_vector(7 downto 0);	-- Switch: '1' is up
	--
	pmod_a	: out std_logic_vector(7 downto 0);	-- logic analyzer
	pmod_b	: out std_logic_vector(3 downto 0);	-- logic analyzer
	pmod_b_clk : out std_logic;			-- logic analyzer clock
	pmod_b_trg : out std_logic;			-- logic analyzer trigger
	--
	led	: out std_logic_vector(7 downto 0)	-- LED: '1' to turn on
    );

    attribute LOC      : string;	-- Pin Location
    attribute IOSTANDARD : string;	-- LVTTL33, LVCMOS33 etc.
    attribute PERIOD : string;		-- clock period

    attribute LOC of clk_100: signal is "Y9";
    attribute IOSTANDARD of clk_100: signal is "LVCMOS33";
    attribute PERIOD of clk_100: signal is "10 ns";

    attribute LOC of swi: signal is "M15 H17 H18 H19 F21 H22 G22 F22";
    attribute IOSTANDARD of swi: signal is "LVCMOS33";

    attribute LOC of led: signal is "U14 U19 W22 V22 U21 U22 T21 T22";
    attribute IOSTANDARD of led: signal is "LVCMOS33";

    attribute LOC of pmod_a: signal is "AB11 AB10 AB9 AA8 Y11 AA11 Y10 AA9";
    attribute IOSTANDARD of pmod_a: signal is "LVCMOS33";

    attribute LOC of pmod_b: signal is "W12 W11 V10 W8";
    attribute IOSTANDARD of pmod_b: signal is "LVCMOS33";

    attribute LOC of pmod_b_clk: signal is "V12";
    attribute IOSTANDARD of pmod_b_clk: signal is "LVCMOS33";

    attribute LOC of pmod_b_trg: signal is "W10";
    attribute IOSTANDARD of pmod_b_trg: signal is "LVCMOS33";

    -- attribute IFD_DELAY_VALUE : string;
    -- attribute IFD_DELAY_VALUE of pmod_b: signal is "8";

end entity top;


architecture RTL of top is
    component ps7_stub
	port (
	    ps_fclk : out std_logic_vector(3 downto 0)
	);
    end component ps7_stub;

    signal fclk : std_logic_vector(3 downto 0);
    signal clk_src : std_logic;
    signal clk : std_logic;

    attribute buffer_type : string;	-- [io]buf[ghr][p]|none
    attribute buffer_type of fclk: signal is "bufg";

begin
    ps7_stub_inst : ps7_stub
    port map ( ps_fclk => fclk );

    clk_src_proc : process(clk_100, fclk, swi)
    begin 
	case swi(2 downto 0) is
	    when "000" => clk_src <= '0';
	    when "001" => clk_src <= '1';
	    when "010" => clk_src <= clk_100;
	    when "011" => clk_src <= clk_100;
	    when "100" => clk_src <= fclk(0);
	    when "101" => clk_src <= fclk(1);
	    when "110" => clk_src <= fclk(2);
	    when "111" => clk_src <= fclk(3);
	    when others => clk_src <= '0';	-- compiler bug
	end case;
    end process;

    clk_proc : process(clk_src, swi)
	variable ratio : natural range 0 to 100000000;
	variable divide : natural range 0 to 100000000;
	variable count : natural range 0 to 255;
	variable trigger : std_logic;
    begin
	case swi(7 downto 4) is
	    when "0000" => ratio := 1 - 1;
	    when "0001" => ratio := 2 - 1;
	    when "0010" => ratio := 5 - 1;
	    when "0011" => ratio := 10 - 1;
	    when "0100" => ratio := 20 - 1;
	    when "0101" => ratio := 50 - 1;
	    when "0110" => ratio := 100 - 1;
	    when "0111" => ratio := 200 - 1;
	    when "1000" => ratio := 1000 - 1;
	    when "1001" => ratio := 2000 - 1;
	    when "1010" => ratio := 5000 - 1;
	    when "1011" => ratio := 10000 - 1;
	    when "1100" => ratio := 100000 - 1;
	    when "1101" => ratio := 1000000 - 1;
	    when "1110" => ratio := 10000000 - 1;
	    when "1111" => ratio := 100000000 - 1;
	    when others => ratio := 0;		-- compiler bug
	end case;

	if rising_edge(clk_src) then
	    if divide = 0 then
		divide := ratio;
		count := count + 1;
	    else
		divide := divide - 1;
	    end if;

	    trigger := '1' when count = 0 else '0';
	end if;

	if falling_edge(clk_src) then
	    if swi(3) = '1' then
		led <= std_logic_vector(to_unsigned(count, 8));
	    else
		led <= (others => '0');
	    end if;

	    pmod_a <= std_logic_vector(to_unsigned(count, 8));
	    pmod_b(3 downto 0) <= (others => '0');
	end if;

	pmod_b_trg <= trigger;
    end process;

    pmod_b_clk <= not clk_src;
end RTL;