---------------------------------------------------------------------------- -- hdmi.vhd -- ZedBoard simple VHDL example -- Version 1.0 -- -- Copyright (C) 2013 H.Poetzl -- -- This program is free software: you can redistribute it and/or -- modify it under the terms of the GNU General Public License -- as published by the Free Software Foundation, either version -- 2 of the License, or (at your option) any later version. -- -- xflow -p xc7z020clg484-1 -wd build -synth xst_vhdl.opt hdmi.prj -- xflow -p xc7z020clg484-1 -wd build -implement balanced.opt -config bitgen.opt hdmi.ngc -- (cd build; promgen -w -b -p bin -o hdmi.bin -u 0 hdmi.bit -data_width 32) -- ---------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.ALL; entity top is port ( clk_100 : in std_logic; -- input clock to FPGA -- sda : inout std_logic; -- HDMI SDA scl : inout std_logic; -- HDMI SCL -- data : out std_logic_vector(15 downto 0); -- HDMI D[15:0] hsync : out std_logic; -- HDMI HSYNC vsync : out std_logic; -- HDMI VSYNC de : out std_logic; -- HDMI DE clk : out std_logic; -- HDMI CLK -- swi : in std_logic_vector(7 downto 0); -- Switch: '1' is up -- led : out std_logic_vector(7 downto 0) -- LED: '1' to turn on ); attribute LOC : string; -- Pin Location attribute IOSTANDARD : string; -- LVTTL33, LVCMOS33 etc. attribute PERIOD : string; -- clock period attribute LOC of clk_100: signal is "Y9"; attribute IOSTANDARD of clk_100: signal is "LVCMOS33"; attribute PERIOD of clk_100: signal is "10 ns"; attribute LOC of sda: signal is "Y16"; attribute IOSTANDARD of sda: signal is "LVCMOS33"; attribute LOC of scl: signal is "AA18"; attribute IOSTANDARD of scl: signal is "LVCMOS33"; attribute LOC of data: signal is "V13 V14 U17 V15 W15 W13 Y15 AA17 AB17 AA16 AB16 AB15 Y14 AA14 AA13 Y13"; attribute IOSTANDARD of data: signal is "LVCMOS33"; attribute LOC of hsync: signal is "V17"; attribute LOC of vsync: signal is "W17"; attribute LOC of de: signal is "U16"; attribute IOSTANDARD of hsync, vsync, de: signal is "LVCMOS33"; attribute LOC of clk: signal is "W18"; attribute IOSTANDARD of clk: signal is "LVCMOS33"; attribute PERIOD of clk: signal is "5ns"; attribute LOC of swi: signal is "M15 H17 H18 H19 F21 H22 G22 F22"; attribute IOSTANDARD of swi: signal is "LVCMOS33"; attribute LOC of led: signal is "U14 U19 W22 V22 U21 U22 T21 T22"; attribute IOSTANDARD of led: signal is "LVCMOS33"; end entity top; architecture RTL of top is component ps7_stub port ( ps_fclk : out std_logic_vector(3 downto 0); -- i2c_sda_i : in std_ulogic; i2c_sda_o : out std_ulogic; i2c_sda_tn : out std_ulogic; -- i2c_scl_i : in std_ulogic; i2c_scl_o : out std_ulogic; i2c_scl_tn : out std_ulogic; -- m_axi_aclk : in std_logic; -- m_axi_aresetn : out std_logic; -- write address m_axi_awid : out std_logic_vector(11 downto 0); m_axi_awaddr : out std_logic_vector(31 downto 0); m_axi_awvalid : out std_logic; m_axi_awready : in std_logic; -- write data m_axi_wdata : out std_logic_vector(31 downto 0); m_axi_wstrb : out std_logic_vector(3 downto 0); m_axi_wvalid : out std_logic; m_axi_wready : in std_logic; -- write response m_axi_bid : in std_logic_vector(11 downto 0); m_axi_bresp : in std_logic_vector(1 downto 0); m_axi_bvalid : in std_logic; m_axi_bready : out std_logic; -- read address m_axi_arid : out std_logic_vector(11 downto 0); m_axi_araddr : out std_logic_vector(31 downto 0); m_axi_arvalid : out std_logic; m_axi_arready : in std_logic; -- read data m_axi_rid : in std_logic_vector(11 downto 0); m_axi_rdata : in std_logic_vector(31 downto 0); m_axi_rresp : in std_logic_vector(1 downto 0); m_axi_rvalid : in std_logic; m_axi_rready : out std_logic ); end component ps7_stub; component IOBUF generic ( CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12; IBUF_DELAY_VALUE : string := "0"; IBUF_LOW_PWR : boolean := TRUE; IFD_DELAY_VALUE : string := "AUTO"; IOSTANDARD : string := "DEFAULT"; SLEW : string := "SLOW" ); port ( O : out std_ulogic; IO : inout std_ulogic; I : in std_ulogic; T : in std_ulogic ); end component IOBUF; signal sda_i : std_ulogic; signal sda_o : std_ulogic; signal sda_tn : std_ulogic; signal sda_t : std_ulogic; signal scl_i : std_ulogic; signal scl_o : std_ulogic; signal scl_tn : std_ulogic; signal scl_t : std_ulogic; signal fclk : std_logic_vector(3 downto 0); attribute buffer_type : string; -- [io]buf[ghr][p]|none attribute buffer_type of fclk: signal is "bufg"; component reg_file generic ( REG_SIZE : integer := 32 ); port ( s_axi_aclk : in std_logic; -- s_axi_aresetn : in std_logic; -- write address s_axi_awaddr : in std_logic_vector(31 downto 0); s_axi_awvalid : in std_logic; s_axi_awready : out std_logic; -- write data s_axi_wdata : in std_logic_vector(31 downto 0); s_axi_wstrb : in std_logic_vector(3 downto 0); s_axi_wvalid : in std_logic; s_axi_wready : out std_logic; -- write response s_axi_bresp : out std_logic_vector(1 downto 0); s_axi_bvalid : out std_logic; s_axi_bready : in std_logic; -- read address s_axi_araddr : in std_logic_vector(31 downto 0); s_axi_arvalid : in std_logic; s_axi_arready : out std_logic; -- read data s_axi_rdata : out std_logic_vector(31 downto 0); s_axi_rresp : out std_logic_vector(1 downto 0); s_axi_rvalid : out std_logic; s_axi_rready : in std_logic; -- reg_0 : out std_logic_vector(REG_SIZE - 1 downto 0); reg_1 : out std_logic_vector(REG_SIZE - 1 downto 0); reg_2 : out std_logic_vector(REG_SIZE - 1 downto 0); reg_3 : out std_logic_vector(REG_SIZE - 1 downto 0); reg_4 : out std_logic_vector(REG_SIZE - 1 downto 0); reg_5 : out std_logic_vector(REG_SIZE - 1 downto 0); reg_6 : out std_logic_vector(REG_SIZE - 1 downto 0); reg_7 : out std_logic_vector(REG_SIZE - 1 downto 0); reg_8 : out std_logic_vector(REG_SIZE - 1 downto 0); reg_9 : out std_logic_vector(REG_SIZE - 1 downto 0) ); end component reg_file; signal axi_aclk : std_logic; signal axi_aresetn : std_logic; signal axi_awid : std_logic_vector(11 downto 0); signal axi_awaddr : std_logic_vector(31 downto 0); signal m_axi_awvalid : std_logic; signal m_axi_awready : std_logic; signal s_axi_awvalid : std_logic; signal s_axi_awready : std_logic; signal axi_wdata : std_logic_vector(31 downto 0); signal axi_wstrb : std_logic_vector(3 downto 0); signal m_axi_wvalid : std_logic; signal m_axi_wready : std_logic; signal s_axi_wvalid : std_logic; signal s_axi_wready : std_logic; signal axi_bid : std_logic_vector(11 downto 0); signal axi_bresp : std_logic_vector(1 downto 0); signal m_axi_bvalid : std_logic; signal m_axi_bready : std_logic; signal s_axi_bvalid : std_logic; signal s_axi_bready : std_logic; signal axi_arid : std_logic_vector(11 downto 0); signal axi_araddr : std_logic_vector(31 downto 0); signal m_axi_arvalid : std_logic; signal m_axi_arready : std_logic; signal s_axi_arvalid : std_logic; signal s_axi_arready : std_logic; signal axi_rid : std_logic_vector(11 downto 0); signal axi_rdata : std_logic_vector(31 downto 0); signal axi_rresp : std_logic_vector(1 downto 0); signal m_axi_rvalid : std_logic; signal m_axi_rready : std_logic; signal s_axi_rvalid : std_logic; signal s_axi_rready : std_logic; signal reg_0 : std_logic_vector(31 downto 0); signal reg_1 : std_logic_vector(31 downto 0); signal reg_2 : std_logic_vector(31 downto 0); signal reg_3 : std_logic_vector(31 downto 0); signal reg_4 : std_logic_vector(31 downto 0); signal reg_5 : std_logic_vector(31 downto 0); signal reg_6 : std_logic_vector(31 downto 0); signal reg_7 : std_logic_vector(31 downto 0); signal reg_8 : std_logic_vector(31 downto 0); signal reg_9 : std_logic_vector(31 downto 0); component data_gen port ( clk : in std_logic; -- total_w : in std_logic_vector(11 downto 0); total_h : in std_logic_vector(11 downto 0); -- disp_w : in std_logic_vector(11 downto 0); disp_h : in std_logic_vector(11 downto 0); -- blank_h : in std_logic_vector(9 downto 0); blank_v : in std_logic_vector(5 downto 0); -- hsync_s : in std_logic_vector(11 downto 0); hsync_e : in std_logic_vector(11 downto 0); -- vsync_s : in std_logic_vector(11 downto 0); vsync_e : in std_logic_vector(11 downto 0); -- data : out std_logic_vector(15 downto 0); hsync : out std_logic; vsync : out std_logic; de : out std_logic; -- frame : out std_logic_vector(7 downto 0) ); end component data_gen; signal frame : std_logic_vector(7 downto 0); begin ps7_stub_inst : ps7_stub port map ( ps_fclk => fclk, i2c_sda_i => sda_i, i2c_sda_o => sda_o, i2c_sda_tn => sda_tn, i2c_scl_i => scl_i, i2c_scl_o => scl_o, i2c_scl_tn => scl_tn, m_axi_aclk => axi_aclk, m_axi_aresetn => axi_aresetn, m_axi_awid => axi_awid, m_axi_awaddr => axi_awaddr, m_axi_awvalid => m_axi_awvalid, m_axi_awready => m_axi_awready, m_axi_wdata => axi_wdata, m_axi_wstrb => axi_wstrb, m_axi_wvalid => m_axi_wvalid, m_axi_wready => m_axi_wready, m_axi_bid => axi_bid, m_axi_bresp => axi_bresp, m_axi_bvalid => m_axi_bvalid, m_axi_bready => m_axi_bready, m_axi_arid => axi_arid, m_axi_araddr => axi_araddr, m_axi_arvalid => m_axi_arvalid, m_axi_arready => m_axi_arready, m_axi_rid => axi_rid, m_axi_rdata => axi_rdata, m_axi_rresp => axi_rresp, m_axi_rvalid => m_axi_rvalid, m_axi_rready => m_axi_rready ); reg_file_inst : reg_file port map ( s_axi_aclk => axi_aclk, s_axi_aresetn => axi_aresetn, s_axi_awaddr => axi_awaddr, s_axi_awvalid => s_axi_awvalid, s_axi_awready => s_axi_awready, s_axi_wdata => axi_wdata, s_axi_wstrb => axi_wstrb, s_axi_wvalid => s_axi_wvalid, s_axi_wready => s_axi_wready, s_axi_bresp => axi_bresp, s_axi_bvalid => s_axi_bvalid, s_axi_bready => s_axi_bready, s_axi_araddr => axi_araddr, s_axi_arvalid => s_axi_arvalid, s_axi_arready => s_axi_arready, s_axi_rdata => axi_rdata, s_axi_rresp => axi_rresp, s_axi_rvalid => s_axi_rvalid, s_axi_rready => s_axi_rready, reg_0 => reg_0, reg_1 => reg_1, reg_2 => reg_2, reg_3 => reg_3, reg_4 => reg_4, reg_5 => reg_5, reg_6 => reg_6, reg_7 => reg_7, reg_8 => reg_8, reg_9 => reg_9 ); -- sda sda_t <= '1' when sda_tn = '0' else '0'; IOBUF_0_inst : IOBUF generic map ( IOSTANDARD => "LVCMOS33" ) port map ( I => sda_o, O => sda_i, T => sda_t, IO => sda ); -- scl scl_t <= '1' when scl_tn = '0' else '0'; IOBUF_1_inst : IOBUF generic map ( IOSTANDARD => "LVCMOS33" ) port map ( I => scl_o, O => scl_i, T => scl_t, IO => scl ); axi_aclk <= clk_100; axi_inter_proc : process(axi_aclk, m_axi_arvalid, m_axi_awvalid, m_axi_rready, m_axi_bready, s_axi_arready, s_axi_awready, s_axi_rvalid, s_axi_bvalid, s_axi_wready, s_axi_wvalid) variable read_req : std_logic; variable read_active : std_logic := '0'; variable read_complete : std_logic; variable write_req : std_logic; variable write_active : std_logic := '0'; variable write_complete : std_logic; variable busy : std_logic := '0'; variable axid : std_logic_vector(11 downto 0); begin read_req := '1' when (m_axi_arvalid = '1') and (write_active = '0') and (busy = '0') else '0'; write_req := '1' when ((m_axi_awvalid = '1') and (read_active = '0') and (busy = '0') and (m_axi_arvalid = '0')) or ((write_active = '1') and (busy = '0')) else '0'; read_complete := '1' when (s_axi_rvalid = '1') and (m_axi_rready = '1') else '0'; write_complete := '1' when (s_axi_bvalid = '1') and (m_axi_bready = '1') else '0'; if rising_edge(axi_aclk) then if axi_aresetn = '0' then read_active := '0'; elsif read_complete = '1' then read_active := '0'; elsif read_req = '1' then read_active := '1'; end if; if axi_aresetn = '0' then write_active := '0'; elsif write_complete = '1' then write_active := '0'; elsif write_req = '1' then write_active := '1'; end if; if (read_complete = '1') or (write_complete = '1') then busy := '0'; elsif ((read_req = '0') and (s_axi_awready = '1') and (m_axi_awvalid = '1')) or ((write_req = '0') and (s_axi_arready = '1') and (m_axi_arvalid = '1')) then busy := '1'; end if; if (read_req = '1') then axid := axi_arid; elsif (write_req = '1') then axid := axi_awid; end if; end if; s_axi_arvalid <= read_req; if (s_axi_arready = '1') and (read_req = '1') then m_axi_arready <= '1'; else m_axi_arready <= '0'; end if; s_axi_awvalid <= write_req; if (s_axi_awready = '1') and (write_req = '1') then m_axi_awready <= '1'; else m_axi_awready <= '0'; end if; if (m_axi_rready = '1') and (read_active = '1') then s_axi_rready <= '1'; else s_axi_rready <= '0'; end if; if (s_axi_rvalid = '1') and (read_active = '1') then m_axi_rvalid <= '1'; else m_axi_rvalid <= '0'; end if; if (m_axi_bready = '1') and (write_active = '1') then s_axi_bready <= '1'; else s_axi_bready <= '0'; end if; if (s_axi_bvalid = '1') and (write_active = '1') then m_axi_bvalid <= '1'; else m_axi_bvalid <= '0'; end if; if s_axi_wready = '1' then m_axi_wready <= '1'; else m_axi_wready <= '0'; end if; if m_axi_wvalid = '1' then s_axi_wvalid <= '1'; else s_axi_wvalid <= '0'; end if; axi_rid <= axid; axi_bid <= axid; end process; clk <= fclk(0); data_gen_inst : data_gen port map ( clk => fclk(0), -- total_w => reg_0(11 downto 0), total_h => reg_1(11 downto 0), -- disp_w => reg_2(11 downto 0), disp_h => reg_3(11 downto 0), -- blank_h => reg_4(9 downto 0), blank_v => reg_5(5 downto 0), -- hsync_s => reg_6(11 downto 0), hsync_e => reg_7(11 downto 0), -- vsync_s => reg_8(11 downto 0), vsync_e => reg_9(11 downto 0), -- data => data, hsync => hsync, vsync => vsync, de => de, -- frame => frame ); vis_proc : process(swi, reg_0, reg_1, reg_2, reg_3, reg_4, reg_5, reg_6, reg_7, reg_8, reg_9) variable idx, pos : natural; begin idx := to_integer(unsigned(swi(3 downto 0))); pos := to_integer(unsigned(swi(7 downto 6))) * 8; case idx is when 0 => led <= reg_0(pos + 7 downto pos); when 1 => led <= reg_1(pos + 7 downto pos); when 2 => led <= reg_2(pos + 7 downto pos); when 3 => led <= reg_3(pos + 7 downto pos); when 4 => led <= reg_4(pos + 7 downto pos); when 5 => led <= reg_5(pos + 7 downto pos); when 6 => led <= reg_6(pos + 7 downto pos); when 7 => led <= reg_7(pos + 7 downto pos); when 8 => led <= reg_8(pos + 7 downto pos); when 9 => led <= reg_9(pos + 7 downto pos); when 15 => led <= swi; when others => led <= frame; end case; end process; end RTL;