----------------------------------------------------------------------------
--  data_gen.vhd
--	ZedBoard simple VHDL example
--	Version 1.0
--
--  Copyright (C) 2013 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
--
----------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.ALL;

entity data_gen is
    port (
	clk	: in std_logic;				-- Data CLK
	--
	total_w	: in std_logic_vector(11 downto 0);	-- Total Width
	total_h	: in std_logic_vector(11 downto 0);	-- Total Heigt
	--
	disp_w	: in std_logic_vector(11 downto 0);	-- Visible Width
	disp_h	: in std_logic_vector(11 downto 0);	-- Visible Height
	--
	blank_h : in std_logic_vector(9 downto 0);	-- H-Blank
	blank_v : in std_logic_vector(5 downto 0);	-- V-Blank
	--
	hsync_s	: in std_logic_vector(11 downto 0);	-- H-Sync Start
	hsync_e	: in std_logic_vector(11 downto 0);	-- H-Sync End
	--
	vsync_s	: in std_logic_vector(11 downto 0);	-- V-Sync Start
	vsync_e	: in std_logic_vector(11 downto 0);	-- V-Sync End
	--
	data	: out std_logic_vector(15 downto 0);	-- Data
	hsync	: out std_logic;			-- HSYNC
	vsync	: out std_logic;			-- VSYNC
	de	: out std_logic;			-- DE
	--
	frame	: out std_logic_vector(7 downto 0)	-- frame number
    );
end entity data_gen;


architecture RTL of data_gen is

    signal hcnt	: unsigned(11 downto 0);
    signal vcnt	: unsigned(11 downto 0);
    signal fcnt : unsigned(7 downto 0);

    signal hb : std_logic;
    signal vb : std_logic;

begin
    gen_proc : process(clk, hcnt, vcnt, hb, vb)
	variable even : boolean;
	variable Y : unsigned(7 downto 0);
	variable Cb : unsigned(7 downto 0);
	variable Cr : unsigned(7 downto 0);
    begin
	if rising_edge(clk) then

	    -- traverse total data area
	    if hcnt = unsigned(total_w) then
		hcnt <= (others => '0');
		if vcnt = unsigned(total_h) then
		    vcnt <= (others => '0');
		    fcnt <= fcnt + 1;
		else
		    vcnt <= vcnt + 1;
		end if;
	    else
		hcnt <= hcnt + 1;
	    end if;

	    -- update hb
	    if (hcnt >= unsigned(blank_h)) and
		(hcnt < unsigned(blank_h) + unsigned(disp_w)) then
		hb <= '0';
	    else
		hb <= '1';
	    end if;

	    -- update vb
	    if (vcnt >= unsigned(blank_v)) and
		(vcnt < unsigned(blank_v) + unsigned(disp_h)) then
		vb <= '0';
	    else
		vb <= '1';
	    end if;

	    -- update hsync
	    if hcnt = unsigned(hsync_s) then
		hsync <= '1';
	    end if;
	    if hcnt = unsigned(hsync_e) then
		hsync <= '0';
	    end if;

	    -- update vsync
	    if vcnt = unsigned(vsync_s) then
		vsync <= '1';
	    end if;
	    if vcnt = unsigned(vsync_e) then
		vsync <= '0';
	    end if;

	    if (hb = '1') or (vb = '1') then
		even := true;
	    else
		even := not even;
	    end if;

	end if;

	-- Y/Cb/Cr
	Y := vcnt(7 downto 0) + hcnt(7 downto 0);
	Cb := hcnt(7 downto 0) + fcnt;
	Cr := vcnt(7 downto 0) + fcnt;

	-- data/de
	if (hb = '1') or (vb = '1') then
	    de <= '0';
	    data <= (others => '0');
	else
	    de <= '1';
	    if even then
		data <= std_logic_vector(Y) & std_logic_vector(Cb);
	    else
		data <= std_logic_vector(Y) & std_logic_vector(Cr);
	    end if;
	end if;

	frame <= std_logic_vector(fcnt);
    end process;
end RTL;