----------------------------------------------------------------------------
--  hdmi_i2c.vhd
--	ZedBoard simple VHDL example
--	Version 1.0
--
--  Copyright (C) 2013 H.Poetzl
--
--	This program is free software: you can redistribute it and/or
--	modify it under the terms of the GNU General Public License
--	as published by the Free Software Foundation, either version
--	2 of the License, or (at your option) any later version.
--
--  xflow -p xc7z020clg484-1 -synth xst_vhdl.opt hdmi_i2c.prj
--  xflow -p xc7z020clg484-1 -implement balanced.opt -config bitgen.opt hdmi_i2c.ngc
--  promgen -w -b -p bin -o hdmi_i2c.bin -u 0 hdmi_i2c.bit -data_width 32
--
----------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;

entity top is
    port (
	sda	: inout std_logic;			-- HDMI SDA
	scl	: inout std_logic;			-- HDMI SCL
	--
	data	: out std_logic_vector(15 downto 0);	-- HDMI D[15:0]
	hsync	: out std_logic;			-- HDMI HSYNC
	vsync	: out std_logic;			-- HDMI VSYNC
	de	: out std_logic;			-- HDMI DE
	clk	: out std_logic				-- HDMI CLK
    );

    attribute LOC      : string;	-- Pin Location
    attribute IOSTANDARD : string;	-- LVTTL33, LVCMOS33 etc.
    attribute PERIOD : string;		-- clock period

    attribute LOC of sda: signal is "Y16";
    attribute LOC of scl: signal is "AA18";
    attribute IOSTANDARD of sda, scl: signal is "LVCMOS33";

    attribute LOC of data: signal is 
	"V13 V14 U17 V15 W15 W13 Y15 AA17 AB17 AA16 AB16 AB15 Y14 AA14 AA13 Y13";
    attribute IOSTANDARD of data: signal is "LVCMOS33";

    attribute LOC of hsync: signal is "V17";
    attribute LOC of vsync: signal is "W17";
    attribute LOC of de: signal is "U16";
    attribute IOSTANDARD of hsync, vsync, de: signal is "LVCMOS33";

    attribute LOC of clk: signal is "W18";
    attribute IOSTANDARD of clk: signal is "LVCMOS33";
    attribute PERIOD of clk: signal is "5ns";

end entity top;


architecture RTL of top is
    component ps7_stub
	port (
	    ps_fclk : out std_logic_vector(3 downto 0);
	    --
	    i2c_sda_i : in std_ulogic;
	    i2c_sda_o : out std_ulogic;
	    i2c_sda_tn : out std_ulogic;
	    --
	    i2c_scl_i : in std_ulogic;
	    i2c_scl_o : out std_ulogic;
	    i2c_scl_tn : out std_ulogic
	);
    end component ps7_stub;

    component IOBUF
	generic (
	    CAPACITANCE : string := "DONT_CARE";
	    DRIVE : integer := 12;
	    IBUF_DELAY_VALUE : string := "0";
	    IBUF_LOW_PWR : boolean := TRUE;
	    IFD_DELAY_VALUE : string := "AUTO";
	    IOSTANDARD : string := "DEFAULT";
	    SLEW : string := "SLOW"
	);
	port (
	    O : out std_ulogic;
	    IO : inout std_ulogic;
	    I : in std_ulogic;
	    T : in std_ulogic
	);
    end component IOBUF;

    signal sda_i : std_ulogic;
    signal sda_o : std_ulogic;
    signal sda_tn : std_ulogic;
    signal sda_t : std_ulogic;

    signal scl_i : std_ulogic;
    signal scl_o : std_ulogic;
    signal scl_tn : std_ulogic;
    signal scl_t : std_ulogic;

    signal fclk : std_logic_vector(3 downto 0);

    attribute buffer_type : string;	-- [io]buf[ghr][p]|none
    attribute buffer_type of fclk: signal is "bufg";

begin
    ps7_stub_inst : ps7_stub
	port map ( ps_fclk => fclk,
		   i2c_sda_i => sda_i, i2c_sda_o => sda_o, i2c_sda_tn => sda_tn,
		   i2c_scl_i => scl_i, i2c_scl_o => scl_o, i2c_scl_tn => scl_tn );

    -- sda
    sda_t <= '1' when sda_tn = '0' else '0';
    IOBUF_0_inst : IOBUF
	generic map ( IOSTANDARD => "LVCMOS33" )
	port map ( I => sda_o, O => sda_i, T => sda_t, IO => sda );

    -- scl
    scl_t <= '1' when scl_tn = '0' else '0';
    IOBUF_1_inst : IOBUF
	generic map ( IOSTANDARD => "LVCMOS33" )
	port map ( I => scl_o, O => scl_i, T => scl_t, IO => scl );

    -- data
    data <= "1111111111111111";
    hsync <= '0';
    vsync <= '0';
    de <= '0';
    clk <= fclk(0);

end RTL;