/*
 */

#ifndef _S3C2410_UDC_H
#define _S3C2410_UDC_H



#define clear_ep0_sst do { \
    	S3C2410_UDC_SETIX(EP0); \
	__raw_writel(0x00, S3C2410_UDC_IN_CSR1_REG); \
} while(0)

#define clear_ep0_se do { \
    	S3C2410_UDC_SETIX(EP0); \
	__raw_maskl(S3C2410_UDC_EP0_CSR_SSE, 0xC0, S3C2410_UDC_IN_CSR1_REG); \
} while(0)

#define clear_ep0_opr do { \
   	S3C2410_UDC_SETIX(EP0); \
	__raw_maskl(S3C2410_UDC_EP0_CSR_SOPKTRDY, 0xC0, S3C2410_UDC_IN_CSR1_REG); \
} while(0)

#define set_ep0_ipr do { \
   	S3C2410_UDC_SETIX(EP0); \
	__raw_maskl(S3C2410_UDC_EP0_CSR_IPKRDY, 0xC0, S3C2410_UDC_IN_CSR1_REG); \
} while(0)

#define set_ep0_de do { \
   	S3C2410_UDC_SETIX(EP0); \
	/* __raw_maskl(S3C2410_UDC_EP0_CSR_DE, 0xC0, S3C2410_UDC_IN_CSR1_REG); */ \
	__raw_writel(S3C2410_UDC_EP0_CSR_DE, S3C2410_UDC_IN_CSR1_REG); \
} while(0)

#define set_ep0_ss do { \
   	S3C2410_UDC_SETIX(EP0); \
	/* __raw_maskl(S3C2410_UDC_EP0_CSR_SENDSTL, 0xC0, S3C2410_UDC_IN_CSR1_REG); */ \
	__raw_writel(S3C2410_UDC_EP0_CSR_SENDSTL, S3C2410_UDC_IN_CSR1_REG);\
} while(0)

#define set_ep0_de_out do { \
   	S3C2410_UDC_SETIX(EP0); \
	__raw_maskl((S3C2410_UDC_EP0_CSR_SOPKTRDY | S3C2410_UDC_EP0_CSR_DE), \
		0xC0, S3C2410_UDC_IN_CSR1_REG); \
} while(0)

#define set_ep0_de_in do { \
   	S3C2410_UDC_SETIX(EP0); \
	__raw_maskl((S3C2410_UDC_EP0_CSR_IPKRDY | S3C2410_UDC_EP0_CSR_DE), \
		0xC0, S3C2410_UDC_IN_CSR1_REG); \
} while(0)

#define clear_stall_ep1_out do { \
   	S3C2410_UDC_SETIX(EP1); \
	__raw_orl(0, S3C2410_UDC_OUT_CSR1_REG); \
} while(0)


#define clear_stall_ep2_out do { \
   	S3C2410_UDC_SETIX(EP2); \
	__raw_orl(0, S3C2410_UDC_OUT_CSR1_REG); \
} while(0)


#define clear_stall_ep3_out do { \
   	S3C2410_UDC_SETIX(EP3); \
	__raw_orl(0, S3C2410_UDC_OUT_CSR1_REG); \
} while(0)

#define clear_stall_ep4_out do { \
   	S3C2410_UDC_SETIX(EP4); \
	__raw_orl(0, S3C2410_UDC_OUT_CSR1_REG); \
} while(0)


#endif